IP Library › Granted Patent US 11,488,864
Granted Patent B2
US 11,488,864 · App. 17/150,557 · Granted Nov 1, 2022

Self-aligned supervia and metal direct etching process to manufacture self-aligned supervia

Inventors: Taeyong Bae (Albany, NY); Hoonseok Seo (Niskayuna, NY); Euibok Lee (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L21/76897H01L21/7682H01L21/76802H01L21/76843H01L21/76877H01L23/528H01L23/5226H01L23/5329
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Quick Facts
Patent No.
US 11,488,864
App. No.
17/150,557
Granted
Nov 1, 2022
Kind
B2
Abstract

A semiconductor device structure includes: at least one inter-metal layer stacked in a vertical direction; and a 1 st via structure penetrating the at least one inter-metal layer, wherein, in the at least one inter-metal layer, a 1 st vertical side of the 1 st via structure does not contact a barrier metal pattern while a 2 nd vertical side of the 1 st via structure opposite to the 1 st vertical side of the 1 st via structure contacts the barrier metal pattern.

Claims (54)

1. A via structure comprising:

at least one inter-metal layer stacked in a vertical direction;

a 1 st via structure penetrating the at least one inter-metal layer;

a lower metal pattern; and

an etch stop layer formed on a top surface of the lower metal pattern, the etch stop layer comprising a 1 st hole through which the top surface of the lower metal pattern is exposed,

wherein, in the at least one inter-metal layer, a 1 st vertical side of the 1 st via structure does not contact a barrier metal pattern while a 2 nd vertical side of the 1 st via structure opposite to the 1 st vertical side of the 1 st via structure contacts the barrier metal pattern,

wherein the 1 st vertical side of the 1 st via structure contacts the at least one inter-metal layer comprising only a single inter-metal layer,

wherein the 2 nd vertical side of the 1 st via structure contacts the at least one inter-metal layer comprising at least two inter-metal layers through the barrier metal pattern,

wherein the 1 st via structure vertically lands on the top surface of the lower metal pattern exposed through the 1 st hole, and

wherein the single inter-metal layer is formed directly on the etch stop layer without overlapping the 1 st hole.

2. The via structure of claim 1 , wherein the 1 st via structure is self-aligned in the 1 st hole formed at the etch stop layer.

3. The via structure of claim 1 , further comprising a 2 nd via structure formed in parallel with the 1 st via structure in a vertical direction,

wherein a 1 st vertical side of the 2 nd via structure does not contact the barrier metal pattern while a 2 nd vertical side of the 2 nd via structure opposite to the 1 st vertical side of the 2 nd via structure contacts the barrier metal pattern.

4. The via structure of claim 3 , wherein the 1 st vertical side of the 2 nd via structure contacts the at least one inter-metal layer comprising the single inter-metal layer, and

wherein the 2 nd vertical side of the 2 nd via structure contacts the at least one inter-metal layer comprising at least two other inter-metal layers through the barrier metal pattern.

5. The via structure of claim 4 , wherein the etch stop layer further comprises a 2 nd hole through which the top surface of the lower metal pattern is exposed, and

wherein the 2 nd via structure vertically land on the top surface of the lower metal pattern exposed through the 2 nd hole.

6. The via structure of claim 5 , wherein the 1 st and 2 nd via structures are self-aligned in the 1 st and 2 nd holes formed at the etch stop layer, respectively.

7. A via structure comprising:

at least one inter-metal layer stacked in a vertical direction;

a 1 st via structure penetrating the at least one inter-metal layer;

a 2 nd via structure formed in parallel with the 1 st via structure in a vertical direction; and

a 3 rd via structure formed between the 1 st and 2 nd via structures in parallel with the 1 st and 2 nd via structures in the vertical direction,

wherein, in the at least one inter-metal layer, a 1 st vertical side of the 1 st via structure and a 1 st vertical side of the 2 nd via structure do not contact a barrier metal pattern while a 2 nd vertical side of the 1 st via structure opposite to the 1 st vertical side of the 1 st via structure and a 2 nd vertical side of the 2 nd via structure opposite to the 1 st vertical side of the 2 nd via structure contact the barrier metal pattern,

wherein an air gap is formed between the 1 st via structure and the 3 rd via structure, and between the 2 nd via structure and the 3 rd via structure, and

wherein another inter-metal layer is formed above the air gap between the 1 st via structure and the 3 rd via structure and between the 2 nd via structure and the 3 rd via structure.

8. The via structure of claim 7 , further comprising a lower metal pattern and an etch stop layer formed on a top surface of the lower metal pattern, the etch stop layer comprising three holes through which the top surface of the lower metal pattern is exposed,

wherein the 1 st to 3 rd via structures vertically land on the top surface of the lower metal pattern exposed through the three holes.

9. A method of forming a via structure, the method comprising:

providing a device structure comprising at least one 1 st inter-metal layer, a lower metal pattern formed below the at least one 1 st inter-metal layer;

etching a section of the at least one 1 st inter-metal layer from top thereof to form a 1 st trench exposing at least a section of a top surface of the lower metal pattern;

filling the 1 st trench with a via metal;

etching at least one section of the via metal from top thereof to form at least one 2 nd trench exposing the top surface of the lower metal pattern so that at least one via structure comprising the via metal is formed at least one side of the at least one 2 nd trench after the etching the at least one section of the via metal; and

filling the at least one 2 nd trench with a 2 nd inter-metal layer.

10. The method of claim 9 , wherein the etching at least one section of the via metal comprises etching at least one middle section of the via metal from top thereof to form the at least one 2 nd trench exposing the top surface of the lower metal pattern so that at least two via structures comprising the via metal are formed on at least two sides of the at least one 2 nd trench after the etching the at least one middle section of the via metal.

11. The method of claim 9 , wherein the filling the 1 st trench with a via metal comprises:

layering a barrier metal pattern on a surface of the 1 st trench; and

filling the via metal in the 1 st trench on which the barrier metal pattern is layered.

12. A method of forming a via structure in a back-end-of-line (BEOL) interconnect structure, the method comprising:

providing a device structure comprising at least one 1 st inter-metal layer, a lower metal pattern formed below the at least one 1 st inter-metal layer, and an etch stop layer formed on a top surface of the lower metal pattern;

etching the at least one 1 st inter-metal layer from top thereof to form a 1 st trench exposing at least one section of the top surface of the lower metal pattern;

filling the 1 st trench with a via metal;

etching at least one section of the via metal from top thereof to form at least one 2 nd trench exposing the etch stop layer on the top surface of the lower metal pattern so that at least one via structure comprising the via metal is formed on at least one side of the at least one 2 nd trench after the etching the at least one section of the via metal; and

filling the at least one 2 nd trench with a 2 nd inter-metal layer.

13. The method of claim 12 , wherein the etching the at least one 1 st inter-metal layer comprises:

forming at least one mask on the at least one 1 st inter-metal layer, and patterning the at least one mask to form at least one opening therein, through photolithography masking;

etching the at least one 1 st inter-metal layer and the etch stop layer through the at least one opening to form at least one via hole including at least one hole at the etch stop layer exposing the top surface of the lower metal pattern;

removing the at least one mask; and

etching the at least one 1 st inter-metal layer at a side of the at least one via hole to form the 1 st trench, of which a bottom comprises the at least one section of the top surface of the lower metal pattern and the etch stop layer.

14. The method of claim 13 , wherein the filling the 1 st trench with a via metal comprises self-aligning the via metal in the at least one hole formed at the etch stop layer.

15. The method of claim 14 , wherein the etching at least one section of the via metal comprises etching at least one middle section of the via metal from top thereof to form the at least one 2 nd trench exposing the at least one section of the top surface of the lower metal pattern so that at least two via structures comprising the via metal are formed on at least two sides of the at least one 2 nd trench after the etching the at least one middle section of the via metal.

16. The method of claim 12 , wherein the filling the 1 st trench with the via metal comprises:

layering a barrier metal pattern on a surface of the 1 st trench; and

filling the via metal in the 1 st trench on which the barrier metal pattern is layered.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2021
From: BAE, TAEYONG; SEO, HOONSEOK; LEE, EUIBOK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 054936/0441 →
Continuity (2)
Provisional Application 63086867 · Oct 2, 2020
Related Publication 20220108921A1 · Apr 7, 2022