Nanosheet transistor bottom isolation
Semiconductor devices and methods of forming the same include forming slanted dielectric structures from a first dielectric material on a substrate, with gaps between adjacent slanted dielectric structures. A first semiconductor layer is grown from the substrate, using a first semiconductor material, including a lower portion that fills the gaps and an upper portion above the first dielectric material. The lower portion of the first semiconductor layer is replaced with additional dielectric material.
1. A semiconductor device, comprising:
a bottom dielectric isolation layer comprising a plurality of slanted dielectrics having a first dielectric material that are separated by directly abutting dielectric fill regions of a second dielectric material, the first dielectric material being a different composition than the second dielectric material;
a plurality of stacks of vertically arranged channel layers formed over the bottom isolation layer; and
a plurality of gate stacks formed on and between the vertically arranged channel layers of respective stacks from the plurality of stacks.
2. The semiconductor device of claim 1 , wherein the first dielectric material is silicon carbonitride and the second dielectric material is silicon nitride.
3. The semiconductor device of claim 1 , wherein at least a portion of a top surface of at least one of the plurality of slanted dielectric structures formed from the first dielectric material vertically overlaps with at least a portion of a bottom surface of a respective adjacent slanted dielectric structure formed from the first dielectric material.
4. The semiconductor device of claim 1 , wherein the vertically arranged channel layers lack threading dislocations.
5. The semiconductor device of claim 1 , wherein the vertically arranged channel layers include stacked semiconductor material layers separated by regions of isolation.
6. The semiconductor device of claim 5 , wherein source and drain regions are present on opposing sides of the stacked semiconductor material layers.
7. The semiconductor device of claim 6 , wherein the source and drain regions provide are in epitaxial relationship with a plurality of the stacked semiconductor material layers to provide merged source and drain regions.
8. The semiconductor device of claim 1 , wherein the plurality of gate stacks include a gate dielectric that wraps around the vertically arranged channel layers.
9. A semiconductor device, comprising:
an isolation layer comprising slanted dielectric structures, wherein slanted dielectric structures are comprised of a first dielectric material and gaps between the slanted dielectric structures are filled with a second dielectric material, and at least a portion of a top surface of at least one of the plurality of slanted dielectric structures formed from the first dielectric material vertically overlaps with at least a portion of a bottom surface of a respective adjacent slanted dielectric structure formed from the first dielectric material;
a plurality of stacked channel layers present on the dielectric layer; and
a plurality of gate stacks present on the stacked channel layers.
10. The semiconductor device of claim 9 , wherein the first dielectric material is silicon carbonitride and the second dielectric material is silicon nitride.
11. The semiconductor device of claim 9 , wherein the stacked channel layers lack threading dislocations.
12. A semiconductor device, comprising:
an isolation layer comprising slanted dielectric structures, wherein slanted dielectric structures are comprised of a first dielectric material and gaps between the slanted dielectric structures are filled with a second dielectric material;
a plurality of stacked channel layers present on the dielectric layer; and
a plurality of gate stacks present on the stacked channel layers.
13. The semiconductor device of claim 12 , wherein the first dielectric material is carbon and nitrogen containing dielectric and the second dielectric material is nitride containing dielectric that is substantially free of carbon.
14. The semiconductor device of claim 12 , wherein the stacked channel layers lack threading dislocations.
15. The semiconductor device of claim 12 , wherein source and drain regions are present on opposing sides of the plurality of stacked channel layers.
16. The semiconductor device of claim 12 , wherein the plurality of gate stacks include a gate dielectric that wraps around the plurality of stacked channel layers.