Accelerating neuron computations in artificial neural networks with dual sparsity

1. A system for accelerating computation of an artificial neural network (ANN), the system comprising:

one or more arithmetic units;

one or more accumulation units; and

one or more processing units coupled with the one or more arithmetic units and the one or more accumulation units, wherein:

the one or more processing units are configured to:

receive a first plurality of first values and a second plurality of second values associated with one or more neurons of the ANN; and

determine a plurality of pairs, wherein each pair of the plurality of pairs has a first value of the first plurality and a second value of the second plurality and wherein the first value and the second value satisfy criteria;

the one or more arithmetic units being configured to perform mathematical operations on pairs of the plurality of pairs to obtain one or more results;

the one of more accumulation units being configured to accumulate the one or more results to obtain accumulated results; and

the one or more processing units being configured to:

determine, based on at least one of the accumulated results, an output of the one or more neurons;

assign a label to a pair of the plurality of pairs, the label being associated with at least one accumulation unit of the one or more accumulation units; and

select, based on the label, an accumulation unit from the one or more accumulation units to accumulate a result of mathematical operations performed on the pair.

2. The system of claim 1 , wherein the one or more processing units are configured to determine that the first value and the second value satisfies the criteria by comparing the first value to a first reference number or comparing the second value to a second reference number.

3. The system of claim 2 , wherein at least one of the first reference number or the second reference number is zero.

4. The system of claim 1 , wherein a number of the one or more accumulation units is larger than a number of the one or more arithmetic units.

5. The system of claim 1 , wherein at least one accumulation unit of the one or more accumulation units is configured to accumulate results of mathematical operations performed by at least two different arithmetic units of the one or more arithmetic units.

6. The system of claim 1 , wherein a count of pairs in the plurality of pairs determined by the one or more processing units is less than a total number of further pairs, the further pairs being obtained by associating each of a first value of the first plurality with each of a second value of the second plurality.

7. The system of claim 1 , wherein the one or more processing units are configured to:

for each first value of the first plurality, generate a first label indicative of whether the first value can be omitted in the computations of the one or more neurons or the first value cannot be omitted in the computations of the one or more neurons; and

for each second value of the second plurality, generate a second label indicative of whether the second value can be omitted in the computations of the one or more neurons or the second value cannot be omitted in the computations of the one or more neurons; and

wherein the first label and the second label are used to configure the one or more accumulation units.

8. The system of claim 7 , wherein:

the first label includes a first binary enable signal;

the second label includes a second binary enable signal; and

wherein the determining that the first value and the second value satisfy criteria includes a Boolean operation on the first binary enable and the second binary enable.

9. The system of claim 1 , wherein one of:

the first plurality of first values includes inputs of the one or more neurons of the ANN and the second plurality of the second values includes weights associated with the inputs of the one or more neurons of the ANN; or

the first plurality of first values includes the weights associated with the inputs of the one or more neurons of the ANN and the second plurality of the second values includes the inputs of the one or more neurons.

10. The system of claim 1 , wherein at least one arithmetic unit of the one or more arithmetic units include at least one electronic circuit configured to perform the mathematical operations.

11. The system of claim 10 , wherein the at least one electronic circuit includes one or more clock signals to trigger the performing of mathematical operations by the at least one electronic circuit.

12. The system of claim 11 , wherein the at least one arithmetic unit is configured to, based on a clock of the one or more clock signals:

at a first cycle of the clock, execute a mathematical operation on a first pair of the plurality of pairs to obtain a first result to be accumulated by a first accumulation unit of the one or more accumulation units;

at a second cycle of the clock, execute a mathematical operation on a second pair of the plurality of pairs to obtain a second result to be accumulated by a second accumulation unit of the one or more accumulation units; and

at a third cycle of the clock, execute a mathematical operation on a third pair of the plurality of pairs to obtain a third result to be accumulated by the first accumulation unit of the one or more accumulation units, wherein the first accumulation unit differs from the second accumulation unit.

13. The system of claim 10 , wherein the electronic circuit includes one or more enable signals to trigger at least one of the accumulation units to accumulate a result of mathematical operations performed by the at least one arithmetic units.

14. The system of claim 1 , wherein the performing the mathematical operations on at least one pair of the plurality of the pairs includes multiplication of a first value of the at least one pair and a second value of the at least one pair.

15. The system of claim 1 , wherein at least one accumulation unit of the one or more accumulation units includes:

at least one adder unit;

at least one multiplexer unit; and

a plurality of register units, wherein the at least one accumulation unit is configured to receive a result from at least one of the arithmetic units and an information on selection, and wherein:

the at least one multiplexer unit is configured to:

select, based on the information of selection, a register unit from the plurality of register units;

provide a value stored in the selected register unit to the adder unit;

the adder unit being configured to perform an addition of the stored value and the result to obtain a sum; and wherein

the sum is stored back to a register unit of the plurality of register units.

16. A method for accelerating computation of an artificial neural network (ANN), the method comprising:

receiving, by one or more processing units coupled with one or more arithmetic units and one or more accumulation units, a first plurality of first values and a second plurality of second values associated with one or more neurons of the ANN;

determining, by the one or more processing units, a plurality of pairs, wherein each pair of the plurality of pairs has a first value of the first plurality and a second value of the second plurality and wherein the first value and the second value satisfy criteria;

performing, by the one or more arithmetic units, mathematical operations on pairs of the plurality of pairs to obtain one or more results;

accumulating, by the one of more accumulation units, the one or more results to obtain accumulated results;

determining, by the one or more processing units and based on at least one of the accumulated results, an output of the one or more neurons;

assigning, by the one or more processing units, a label to a pair of the plurality of pairs, the label being associated with at least one accumulation unit of the one or more accumulation units; and

selecting, by the one or more processing units and based on the label, an accumulation unit from the one or more accumulation units to accumulate a result of mathematical operations performed on the pair.

17. The method of claim 16 , wherein the determining that the first value and the second value satisfy the criteria includes comparing the first value to a first reference number or comparing the second value to a second reference number.

18. A system for accelerating computation of an artificial neural network (ANN), the system comprising:

one or more arithmetic units;

one or more accumulation units; and

one or more processing units coupled with the one or more arithmetic units and the one or more accumulation units, wherein:

the one or more processing units are configured to:

receive a first plurality of first values and a second plurality of second values associated with one or more neurons of the ANN; and

determine a plurality of pairs, wherein each pair of the plurality of pairs has a first value of the first plurality and a second value of the second plurality and wherein the first value and the second value satisfy criteria;

the one or more arithmetic being configured to perform mathematical operations on the pairs of the plurality of pairs to obtain one or more results; and

the one or more processing units being configured to obtain accumulated results by:

for each pair of the plurality of pairs:

selecting, based on a label assigned to the pair, an accumulation unit;

causing the selected accumulation unit to accumulate a result of one or more results corresponding to the pair; and

determine, based on the accumulated results, an output of the one or more neurons.