Semiconductor device and test method thereof

1. A semiconductor device, comprising:

first to n-th through-electrodes;

first to n-th through-electrode driving circuits suitable for charging the first to n-th through-electrodes to a first voltage level, or discharging the first to n-th through-electrodes to a second voltage level; and

first to n-th error detection circuits, each suitable for storing the first voltage level or the second voltage level of a corresponding through-electrode of the first to n-th through-electrodes as a down-detection signal and an up-detection signal, and outputting a corresponding error detection signal of first to n-th error detection signals by sequentially masking the down-detection signal and the up-detection signal.

2. The semiconductor device of claim 1 , further comprising:

first to n-th shifting circuits, each suitable for storing an error detection signal outputted from a corresponding one of the first to n-th error detection circuits, or a shifting signal outputted from a previous-positioned shifting circuit, and providing the stored signal as the shifting signal to a next-positioned shifting circuit, according to a selection signal and a shifting clock.

3. The semiconductor device of claim 2 , wherein each of the first to n-th shifting circuits includes:

a selector suitable for selecting one of the error detection signal and the shifting signal in response to the selection signal; and

a shifter suitable for latching an output of the selector and providing the latched signal as the shifting signal to the next-positioned shifting circuit, in response to the shifting clock.

4. The semiconductor device of claim 1 , further comprising:

a first compression circuit suitable for compressing the first to n-th error detection signals to output a first compression signal, when the first to n-th through-electrodes are charged to the first voltage level; and

a second compression circuit suitable for compressing the first to n-th error detection signals to output a second compression signal, when the first to n-th through-electrodes are discharged to the second voltage level.

5. The semiconductor device of claim 4 ,

wherein the first compression circuit outputs the first compression signal by performing a logic AND operation on the first to n-th error detection signals, and

wherein the second first compression circuit outputs the second compression signal by performing a logic OR operation on the first to n-th error detection signals.

6. The semiconductor device of claim 1 , wherein each of the first to n-th error detection circuits includes:

a down-latch circuit suitable for storing the first voltage level or the second voltage level of the corresponding through-electrode as the down-detection signal in response to a down-scan signal and a latch signal;

an up-latch circuit suitable for storing the first voltage level or the second voltage level of the corresponding through-electrode as the up-detection signal in response to an up-scan signal and the latch signal;

a decision circuit suitable for generating the corresponding error detection signal based on the down-detection signal and the up-detection signal; and

a masking circuit suitable for providing the down-detection signal and the up-detection signal to the decision circuit by sequentially masking the down-detection signal outputted from the down-latch circuit and the up-detection signal outputted from the up-latch circuit.

7. The semiconductor device of claim 6 , wherein the down-latch circuit includes:

a first transmitter suitable for transferring the first voltage level or the second voltage level of the corresponding through-electrode based on the down-scan signal and the latch signal; and

a first latch suitable for latching the first voltage level or the second voltage level of the corresponding through-electrode transferred from the first transmitter as the down-detection signal.

8. The semiconductor device of claim 6 , wherein the up-latch circuit includes:

a second transmitter suitable for transferring the first voltage level or the second voltage level of the corresponding through-electrode based on the up-scan signal and the latch signal; and

a second latch suitable for latching the first voltage level or the second voltage level of the corresponding through-electrode transferred from the second transmitter as the up-detection signal.

9. The semiconductor device of claim 6 , wherein the masking circuit includes:

a down masking circuit suitable for masking the down-detection signal according to a down masking signal; and

an up-masking circuit suitable for masking the up-detection signal according to an up-masking signal,

wherein the down masking signal and the up-masking signal are sequentially activated.

10. The semiconductor device of claim 1 , wherein each of the first to n-th through-electrode driving circuits includes:

a pull-up driver suitable for pulling up the corresponding through-electrode to the first voltage level according to a pull-up driving signal; and

a pull-down driver suitable for pulling down the corresponding through-electrode to the second voltage level according to a pull-down driving signal.

11. A test method of a semiconductor device, comprising:

outputting a plurality of error detection signals by storing a first voltage level of each of a plurality of through-electrodes as an up-detection signal while masking a down-detection signal, when charging the plurality of through-electrodes to the first voltage level;

outputting the plurality of error detection signals by storing the first voltage level of each of the plurality of through-electrodes as the down-detection signal while masking the up-detection signal, when charging the plurality of through-electrodes to the first voltage level;

outputting the error detection signals by storing a second voltage level of each of the plurality of through-electrodes as the up-detection signal while masking the down-detection signal, when discharging the plurality of through-electrodes to the second voltage level; and

outputting the error detection signals by storing the second voltage level of each of the plurality of through-electrodes as the down-detection signal while masking the up-detection signal, when discharging the plurality of through-electrodes to the second voltage level.

12. The test method of claim 11 , further comprising:

sequentially shifting the error detection signals to output the shifted signal, according to a selection signal and a shifting clock.

13. The test method of claim 11 , further comprising:

compressing the error detection signals to output a first compression signal, when the plurality of through-electrodes are charged to the first voltage level; and

compressing the error detection signals to output a second compression signal, when the plurality of through-electrodes are discharged to the second voltage level.

14. The test method of claim 13 ,

wherein the first compression signal is generated by performing a logic AND operation on the error detection signals, and

wherein the second compression signal is generated by performing a logic OR operation on the error detection signals.

15. A semiconductor device, comprising:

a plurality of through-electrodes;

a through-electrode driving circuit suitable for charging the plurality of through-electrodes to a first voltage level, or discharging the plurality of through-electrodes to a second voltage level;

a down-latch circuit suitable for storing the first voltage level or the second voltage level of each of the plurality of through-electrodes as a down-detection signal in response to a down-scan signal and a latch signal;

an up-latch circuit suitable for storing the first voltage level or the second voltage level of each of the plurality of through-electrodes as an up-detection signal in response to an up-scan signal and the latch signal;

a masking circuit suitable for sequentially masking the down-detection signal and the up-detection signal; and

a decision circuit suitable for generating a plurality of error detection signals based on the down-detection signal and the up-detection signal, which are outputted from the masking circuit.

16. The semiconductor device of claim 15 , further comprising:

a plurality of shifting circuits, each suitable for storing a corresponding one of the error detection signals, or a shifting signal outputted from a previous-positioned shifting circuit according to a selection signal, and providing the stored signal as a shifting signal to a next-positioned shifting circuit, according to a shifting clock.

17. The semiconductor device of claim 16 , wherein each of the shifting circuits includes:

a selector suitable for selecting one of the corresponding error detection signal and the shifting signal in response to the selection signal; and

a shifter suitable for latching an output of the selector and providing the latched signal as the shifting signal to the next-positioned shifting circuit, in response to the shifting clock.

18. The semiconductor device of claim 15 , further comprising:

a first compression circuit suitable for compressing the error detection signals to output a first compression signal, when the plurality of through-electrodes are charged to the first voltage level; and

a second compression circuit suitable for compressing the error detection signals to output a second compression signal, when the plurality of through-electrodes are discharged to the second voltage level.

19. The semiconductor device of claim 18 ,

wherein the first compression circuit outputs the first compression signal by performing a logic AND operation on the error detection signals, and

wherein the second first compression circuit outputs the second compression signal by performing a logic OR operation on the error detection signals.

20. The semiconductor device of claim 15 , wherein the masking circuit includes:

a down masking circuit suitable for masking the down-detection signal according to a down masking signal; and

an up-masking circuit suitable for masking the up-detection signal according to an up-masking signal,

wherein the down masking signal and the up-masking signal are sequentially activated.

21. A method for testing a plurality of semiconductor chips, each comprising a through-electrode and an error detection circuit for detecting a defect of the through-electrode, the method comprising:

driving the respective through-electrode with predetermined voltage levels;

passing the predetermined voltage levels through the respective error detection circuit to generate detection signals;

detecting a defect of the respective error detection circuit based on logic levels of the detection signals;

stacking the plurality of semiconductor chips in a vertical direction;

passing a source current through the through-electrodes of the stacked semiconductor chips in a downward direction of the stacked semiconductor chips to perform a down-scan operation;

passing a source current through the through-electrodes of the stacked semiconductor chips in an upward direction of the stacked semiconductor chips to perform an up-scan operation; and

determining a defect of the through-electrodes by the error detection circuits based on the down and up-scan operations.

22. The method of claim 21 , wherein the predetermined voltage levels include a first voltage level and a second voltage level greater than the first voltage level by a predetermined voltage,

the respective error detection circuit is provided with the first voltage level to generate a first detection signal,

the respective error detection circuit is provided with the second voltage level to generate a second detection signal, and

the defect of the respective error detection circuit is determined based on a logic level of each of the first and second detection signals.