Interconnect structure in semiconductor devices

1. A device comprising:

a gate stack disposed over a substrate, the gate stack oriented lengthwise along a first direction;

a first metallization layer disposed over the gate stack, the first metallization layer including first metal features disposed in a first dielectric layer, the first metal features having a first thickness, the first thickness being measured in a second direction that is perpendicular to a top surface of the substrate;

a second metallization layer disposed over the first metallization layer, the second metallization layer including second metal features disposed in a second dielectric layer, the second metal features oriented lengthwise along the first direction and having a second thickness, the second thickness measured in the second direction;

a third metallization layer disposed over the second metallization layer, the third metallization layer including third metal features disposed in a third dielectric layer, the third metal features having a third thickness, the third thickness measured in the second direction, wherein the second thickness is smaller than both the first and the third thicknesses;

a first via feature interfacing with the gate stack and one of the first metal features;

a second via feature interfacing with one of the first metal features and one of the second metal features; and

a third via feature interfacing with one of the second metal features and one of the third metal features.

2. The device of claim 1 , wherein the first metal features and the third metal features are oriented lengthwise along the second direction that is substantially perpendicular to the first direction.

3. The device of claim 1 , wherein a ratio of the second thickness to the first thickness is in a range from about 0.5 to about 0.95.

4. The device of claim 1 , wherein a ratio of the second thickness to the third thickness is in a range from about 0.5 to about 0.95.

5. The device of claim 1 , wherein the gate stack includes a plurality of gate stacks oriented lengthwise along the first direction,

wherein the plurality of gate stacks are spaced from each other with a first pitch, and

wherein the second metal features are spaced from each other with a second pitch that is different than the first pitch.

6. The device of claim 5 , wherein the second pitch is less than the first pitch.

7. A device comprising:

a gate stack disposed over a substrate;

a first metallization layer disposed over and electrically coupled to the gate stack, the first metallization layer including first metal features disposed in a first dielectric layer, the first metal features having a first thickness, the first thickness being measured in a first direction perpendicular to a top surface of the substrate;

a second metallization layer disposed over and interfacing with the first metallization layer, the second metallization layer including second metal features disposed in a second dielectric layer, the second metal features having a second thickness measured in the first direction, the second thickness being less than the first thickness;

a third metallization layer disposed over and interfacing with the second metallization layer, the third metallization layer including third metal features disposed in a third dielectric layer, the third metal features having a third thickness, the third thickness measured in the first direction and being different than the second thickness;

a first via feature interfacing with the gate stack and one of the first metal features;

a second via feature interfacing with one of the first metal features and one of the second metal features; and

a third via feature interfacing with one of the second metal features and one of the third metal features.

8. The device of claim 7 , wherein the first metal features are oriented lengthwise substantially perpendicular to the second metal features,

wherein the third metal features are oriented lengthwise substantially parallel to the first metal features, and

wherein the gate stack is oriented lengthwise substantially parallel to the second metal features.

9. The device of claim 7 , wherein the first metal features are oriented lengthwise substantially perpendicular to the second metal features,

wherein the third metal features are oriented lengthwise substantially parallel to the first metal features, and

wherein the gate stack is oriented lengthwise substantially perpendicular to the second metal features.

10. The device of claim 7 , wherein the third thickness is greater than the second thickness, and

wherein the first thickness and the third thickness are about the same.

11. The device of claim 7 , wherein the first via feature is shorter than the second via feature, and

wherein the second via feature is shorter than the third via feature.

12. The device of claim 7 , further comprising a semiconductor fin feature disposed on the substrate, and

wherein the gate stack interfaces with the semiconductor fin feature; and

wherein the semiconductor fin feature is oriented lengthwise substantially perpendicular to the gate stack.

13. The device of claim 7 , wherein the first dielectric layer has a fourth thickness measured in the first direction, and

wherein the second dielectric layer has a fifth thickness measured in the first direction, the fifth thickness being less than the fourth thickness.

14. A device comprising:

semiconductor fins disposed over a substrate;

gate stacks disposed over the semiconductor fins;

a first metallization layer disposed over the gate stacks, the first metallization layer including first metal features disposed in a first dielectric layer, the first metal features oriented lengthwise along a first direction and having a first thickness, the first thickness measured in a second direction that is perpendicular to a top surface of the substrate, the first direction being substantially perpendicular to the second direction;

a second metallization layer disposed directly on the first metallization layer, the second metallization layer including second metal features disposed in a second dielectric layer, the second metal features being oriented lengthwise along a third direction that is substantially perpendicular to the first direction, wherein the second metal features have a second thickness in the second direction that is less than the first thickness;

a first via feature interfacing with one of the gate stacks and one of the first metal features; and

a second via feature interfacing with one of the first metal features and one of the second metal features.

15. The device of claim 14 , further comprising a third metallization layer disposed directly on the second metallization layer, the third metallization layer including third metal features disposed in a third dielectric layer, the third metal features being oriented lengthwise along the first direction, wherein the third metal features have a third thickness in the second direction that is greater than the second thickness.

16. The device of clam 15 , further comprising a third via feature interfacing with one of the second metal features and one of the third metal features.

17. The device of claim 16 , wherein the first via feature is formed of a different material than the first metal feature.

18. The device of claim 15 , wherein a ratio of the second thickness to the first thickness is in a range from about 0.5 to about 0.95,

wherein a ratio of the second thickness to the third thickness is in a range from about 0.5 to about 0.95, and

wherein the first and the third thicknesses are about the same.

19. The device of claim 15 , wherein a ratio of the second thickness to the first thickness is in a range from about 0.8 to about 0.9,

wherein a ratio of the second thickness to the third thickness is in a range from about 0.8 to about 0.9.

20. The device of claim 14 , wherein the gate stacks include at least one gate stack coupled to a fixed voltage.