Three-dimensional semiconductor memory device

1. A three-dimensional (3D) semiconductor memory device comprising:

a first stack structure block comprising first stack structures arranged side by side in a first direction on a substrate;

a second stack structure block comprising second stack structures arranged side by side in the first direction on the substrate;

a separation structure disposed on the substrate comprising a mold layer stack of first mold layers and second mold layers that are interleaved with one another, the mold layer stack being positioned between a first end portion of the first stack structure block and a first end portion of the second stack structure block; and

a contact plug penetrating the separation structure,

wherein a bottom surface of the contact plug is in contact with the substrate,

wherein the first end portion is flat and extends vertically from the bottom of the first stack structure block to the top of the first stack structure block,

wherein the first end portion of the second stack structure block is flat and extends vertically from the bottom of the second stack structure block to the top of the second stack structure block,

wherein the first stack structure block has a second end portion that is at an opposite side of the first stack structure block from the first end portion of the first stack structure block,

wherein the second stack structure block has a second end portion that is at an opposite side of the second stack structure block from the first end portion of the second stack structure block, and

wherein the second end portions of the first and second stack structure blocks have stair structures.

2. The 3D semiconductor memory device of claim 1 , wherein the bottom surface of the contact plug is disposed below the top surface of the substrate.

3. The 3D semiconductor memory device of claim 1 , further comprising a plurality of contact plugs penetrating the separation structure and being in contact with the substrate, the plurality of contact plugs including the contact plug,

wherein the plurality of contact plugs includes first contact plugs and second contact plugs,

wherein the first contact plugs are arranged along a first sidewall of the first stack structure block, which is in contact with the separation structure, and

wherein the second contact plugs are arranged along a first sidewall of the second stack structure block, which is in contact with the separation structure.

4. The 3D semiconductor memory device of claim 1 , wherein the separation structure further comprises:

a first separation layer between the first stack structure block and the first and second mold layers;

a second separation layer between the second stack structure block and the first and second mold layers; and

a plurality of contact plugs penetrating the separation structure and being in contact with the substrate, the plurality of contact plugs including the contact plug,

wherein the plurality of contact plugs includes first contact plugs and second contact plugs,

wherein the first contact plugs are arranged along the first separation layer, and

wherein the second contact plugs are arranged along the second separation layer.

5. The 3D semiconductor memory device of claim 4 , wherein the first and second separation layers are formed of the same material as the first mold layers or the second mold layers.

6. The 3D semiconductor memory device of claim 1 ,

wherein each of the first stack structures comprises gate electrodes and insulating patterns that are interleaved with one another,

wherein each of the first mold layers are disposed at the same level as a corresponding insulating pattern, and

wherein each of the second mold layers are disposed at the same level as a corresponding gate electrode.

7. The 3D semiconductor memory device of claim 1 ,

wherein the first end portion of the first stack structure block is in contact with the separation structure, and

wherein the first end portion of the second stack structure block is in contact with the separation structure.

8. The 3D semiconductor memory device of claim 1 ,

wherein the 3D semiconductor memory device further comprises an interlayer insulating layer, and

wherein the interlayer insulating layer is in contact with the second end portion of the first stack structure block and the second end portion of the second stack structure block.

9. The 3D semiconductor memory device of claim 1 ,

wherein each of the first stack structures comprises gate electrodes, the 3D semiconductor memory device comprises:

cell contact plugs being in contact with end portions of the gate electrodes,

wherein the contact plug is formed of the same material as the cell contact plugs.

10. The 3D semiconductor memory device of claim 1 , further comprising:

a lower substrate disposed under the substrate;

a peripheral circuit structure disposed at the lower substrate, the peripheral circuit structure comprising a transistor, an interconnection conductor, and a via; and

a peripheral contact plug penetrating the separation structure and the substrate and electrically connected to the transistor.

11. A three-dimensional (3D) semiconductor memory device comprising:

a first stack structure block comprising first stack structures arranged side by side in a first direction on a first substrate;

a second stack structure block comprising second stack structures arranged side by side in the first direction on the first substrate;

a separation structure disposed on the first substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers;

a first contact plug penetrating the separation structure and the first substrate;

a second contact plug penetrating the separation structure and electrically connected to the first substrate; and

a connection line electrically connecting the first contact plug and the second contact plug.

12. The 3D semiconductor memory device of claim 11 , further comprising:

a second substrate disposed under the first substrate; and

a peripheral circuit structure disposed at the second substrate and comprising a transistor,

wherein a lower portion of the first contact plug is disposed in the peripheral circuit structure and is electrically connected to the transistor.

13. The 3D semiconductor memory device of claim 11 , wherein a bottom surface of the second contact plug is in contact with the first substrate.

14. A three-dimensional (3D) semiconductor memory device comprising:

a first stack structure block comprising first stack structures arranged side by side in a first direction on a substrate, the first stack structure block including a first end portion that is flat and vertically extends above the substrate and including a second end portion that is opposite to the first end portion in a second direction, the second direction being perpendicular to the first direction;

a second stack structure block comprising second stack structures arranged side by side in the first direction on the first substrate, the second stack structure block including a first end portion that is flat and vertically extends above the substrate and including a second end portion that is opposite to the first end portion in the second direction;

a separation structure disposed on the substrate and disposed on a first sidewall of the first end portion of the first stack structure block and between the first end portions of the first and second stack structure blocks; and

first contact plugs penetrating the separation structure and arranged along the first sidewall of the first end portion,

wherein end portions of each of the first stick structures at the second end portion of the first stack structure block and of each of the second stack structures at the second end portion of the second stack structure block have a stair structure.

15. The 3D semiconductor memory device of claim 14 ,

wherein the first stack structure block further includes a third end portion that is flat and vertically extends above the substrate,

wherein the first sidewall of the first end portion is parallel to the first direction when viewed in a plan view, and

wherein a sidewall of the third end portion is parallel to the second direction.

16. The 3D semiconductor memory device of claim 14 , wherein the separation structure comprises:

a mold structure disposed on the substrate and disposed on the first sidewall of the first end portion of the first stack structure block; and

a separation layer disposed between the mold structure and the first stack structure block,

wherein the mold structure comprises:

a mold layer stack of first mold layers and second mold layers that are interleaved with one another.

17. The 3D semiconductor memory device of claim 14 , further comprising:

transistors disposed under the substrate;

second contact plugs penetrating the separation structure and the substrate and electrically connected to the transistors; and

connection lines each electrically connecting a corresponding one of the first contact plugs and a corresponding one of the second contact plugs.

18. The 3D semiconductor memory device of claim 14 ,

wherein the first stack structure block further includes: a second end portion opposite to the first end portion in a second direction different from the first direction; and a third end portion and a fourth end portion which are disposed between the first end portion and the second end portion and are opposite to each other in the first direction,

the 3D semiconductor memory device further comprising:

an interlayer insulating layer surrounding a second sidewall of the second end portion, a third sidewall of the third end portion, and a fourth sidewall of the fourth end portion; and

second contact plugs penetrating the interlayer insulating layer,

wherein the second contact plugs are arranged along the second sidewall of the second end portion, the third sidewall of the third end portion, and the fourth sidewall of the fourth end portion.

19. The 3D semiconductor memory device of claim 14 ,

wherein the first stack structure block further includes: a second end portion opposite to the first end portion in a second direction intersecting the first direction; and a third end portion and a fourth end portion which are disposed between the first end portion and the second end portion and are opposite to each other in the first direction,

wherein the separation structure extends onto a third sidewall of the third end portion,

the 3D semiconductor memory device further comprising:

an interlayer insulating layer surrounding a second sidewall of the second end portion and a fourth sidewall of the fourth end portion; and

second contact plugs penetrating the interlayer insulating layer,

wherein the first contact plugs are arranged along the first sidewall of the first end portion and the third sidewall of the third end portion, and

wherein the second contact plugs are arranged along the second sidewall of the second end portion and the fourth sidewall of the fourth end portion.