Semiconductor memory device and method of fabricating the same

1. A semiconductor memory device, comprising:

a substrate;

a plurality of electrode structures on the substrate, each of the plurality of electrode structures including horizontal electrodes stacked on each other on the substrate;

vertical electrodes between the electrode structures and extending along the horizontal electrodes;

first contacts connected to the horizontal electrodes at end portions of the plurality of electrode structures;

second contacts connected to upper portions of the vertical electrodes; and

a first interconnection structure connected to top surfaces of the second contacts, the first interconnection structure including first sub-interconnection lines and second sub-interconnection lines at a same level over the substrate,

the first sub-interconnection lines extending in a first direction and contacting the top surfaces of the second contacts; and

the second sub-interconnection lines extending in a second direction crossing the first direction, the second sub-interconnection lines being in contact with the first sub-interconnection lines.

2. The semiconductor memory device of claim 1 , wherein the first contacts have top surfaces that are positioned at substantially a same level as the top surfaces of the second contacts.

3. The semiconductor memory device of claim 1 , wherein a width of each of the second contacts is greater in the first direction than in the second direction.

4. The semiconductor memory device of claim 1 , wherein a separation distance between the second contacts in the first direction is greater than a separation distance between the first contacts in the first direction.

5. The semiconductor memory device of claim 4 , wherein the separation distance between the second contacts in the first direction is 10 to 20 times the separation distance between the first contacts in the first direction.

6. The semiconductor memory device of claim 1 , wherein the first interconnection structure has a grid shape when viewed in a plan view.

7. The semiconductor memory device of claim 1 , further comprising:

vertical structures penetrating the plurality of electrode structures, the vertical structures including channel patterns, wherein

the first sub-interconnection lines overlap the horizontal electrodes, and

the second sub-interconnection lines overlap with the vertical structures.

8. The semiconductor memory device of claim 1 , further comprising:

a second interconnection structure on the first interconnection structure, wherein

the second interconnection structure includes third sub-interconnection lines and fourth sub-interconnection lines,

the third sub-interconnection lines overlap the first sub-interconnection lines and extend parallel to the first sub-interconnection lines,

the fourth sub-interconnection lines overlap the second sub-interconnection lines and extend parallel to the second sub-interconnection lines.

9. The semiconductor memory device of claim 8 , further comprising:

first vias connecting the second sub-interconnection lines to the fourth sub-interconnection lines.

10. The semiconductor memory device of claim 8 , further comprising:

vertical structures penetrating the plurality of electrode structures; and

studs coupled to upper portions of the vertical structures,

wherein a top surface of the second interconnection structure is positioned at substantially a same level as top surfaces of the studs.

11. The semiconductor memory device of claim 10 , further comprising:

second vias on the second interconnection structure;

third interconnection lines that extend in the second direction and connect to the studs through the second vias; and

fourth interconnection lines that extend in the second direction and connect to the second interconnection structure through the second vias, wherein

a width of each of the fourth interconnection lines in the first direction is greater than a width of each of the third interconnection lines in the first direction.

12. The semiconductor memory device of claim 1 , further comprising:

a peripheral transistor; and

third contacts, wherein

the semiconductor memory device includes a cell array region and a peripheral circuit region,

the plurality of electrode structures are in the cell array region,

the peripheral transistor is in the peripheral circuit region,

the third contacts are connected to the peripheral transistor, and

the third contacts have top surfaces that are positioned at substantially a same level as the top surfaces of the second contacts.

13. The semiconductor memory device of claim 1 , wherein the first contacts and the second contacts include spacer patterns enclosing side surfaces thereof.

14. The semiconductor memory device of claim 13 , further comprising:

a peripheral transistor;

an interlayered insulating layer covering the peripheral transistor; and

third contacts that penetrate the interlayered insulating layer and are connected to the peripheral transistor, wherein

the semiconductor memory device includes a cell array region and a peripheral circuit region,

the electrode structures are in the cell array region,

the peripheral transistor is in the peripheral circuit region,

the third contacts include a metal layer and a barrier layer covering a side surface of the metal layer, and

the barrier layer contacts the interlayered insulating layer.

15. A semiconductor memory device, comprising:

a substrate;

a plurality of electrode structures on the substrate, each of the plurality of electrode structures including horizontal electrodes stacked on each other on the substrate;

vertical electrodes between the electrode structures and extending along the horizontal electrodes, the vertical electrodes extending in a first direction;

first contacts connected to the horizontal electrodes at end portions of the plurality of electrode structures;

second contacts connected to upper portions of the vertical electrodes,

top surfaces of the second contacts being positioned at substantially a same level as top surfaces of the first contacts, and

a separation distance between the second contacts in the first direction being greater than a separation distance between the first contacts in the first direction; and

a first interconnection structure connected to the top surfaces of the second contacts.

16. The semiconductor memory device of claim 15 , wherein

the first interconnection structure includes first sub-interconnection lines and second sub-interconnection lines,

the first sub-interconnection lines extend in the first direction and contact with the top surfaces of the second contacts,

the second sub-interconnection lines extend in a second direction that crosses the first direction, and

the second sub-interconnection lines contact the first sub-interconnection lines.

17. The semiconductor memory device of claim 16 , further comprising:

a second interconnection structure on the first interconnection structure, wherein

the second interconnection structure includes third sub-interconnection lines and fourth sub-interconnection lines,

the third sub-interconnection lines overlap with the first sub-interconnection lines and are extend parallel to the first sub-interconnection lines, and

the fourth sub-interconnection lines overlap with the second sub-interconnection lines and extend parallel to the second sub-interconnection lines.

18. The semiconductor memory device of claim 15 , further comprising:

a peripheral transistor; and

third contacts connected to the peripheral transistor, wherein

the semiconductor memory device includes a cell array region and a peripheral circuit region,

the plurality of electrode structures are in the cell array region,

the peripheral transistor is in the peripheral circuit region, and

the third contacts have top surfaces that are positioned at substantially a same level as the top surfaces of the second contacts.

19. The semiconductor memory device of claim 15 , further comprising:

a peripheral transistor;

an interlayered insulating layer covering the peripheral transistor; and

third contacts penetrating the interlayer insulating layer and connecting to the peripheral transistor, wherein

the first contacts and the second contacts include spacer patterns enclosing side surfaces thereof,

the semiconductor memory device includes a cell array region and a peripheral circuit region,

the plurality of electrode structures are in the cell array region,

the peripheral transistor is in the peripheral circuit region,

the third contacts include a metal layer and a barrier layer covering a side surface of the metal layer, and

the barrier layer contacts the interlayered insulating layer.

20. A semiconductor memory device, comprising:

a substrate including a cell array region and a peripheral circuit region;

a plurality of electrode structures on the substrate, each of the plurality of electrode structures including horizontal electrodes stacked on each other on the substrate;

a peripheral transistor in the peripheral circuit region;

vertical structures penetrating the plurality of electrode structures;

studs connected to upper portions of the vertical structures;

vertical electrodes between the plurality of electrode structures, the vertical electrodes extending along the horizontal electrodes and in a first direction;

first contacts connected to the horizontal electrodes at end portions of the plurality of electrode structures;

second contacts connected to upper portions of the vertical electrodes;

extension pads connected to top surfaces of the first contacts;

third contacts connected to the peripheral transistor, top surfaces of the third contacts being positioned at a same level as the top surfaces of the first contacts and top surfaces of the second contacts;

peripheral pads connected to top surfaces of the third contacts;

a first interconnection structure connected to top surfaces of the second contacts, a top surface of the first interconnection structure being positioned at substantially a same level as top surfaces of the extension pads and top surfaces of the peripheral pads; and

a second interconnection structure on the first interconnection structure and connected to the first interconnection structure through first vias, a top surface of the second interconnection structures being positioned at substantially a same level as top surfaces of the studs.