Substrate integrated thin film capacitors using amorphous high-k dielectrics
Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.
1. An electronic package, comprising:
a dielectric layer; and
a capacitor on the dielectric layer, wherein the capacitor comprises:
a first electrode disposed over the dielectric layer;
a capacitor dielectric layer over the first electrode, wherein the capacitor
dielectric layer is an amorphous dielectric layer; and
a second electrode over the capacitor dielectric layer, wherein the first electrode and the second electrode comprise interdigitated portions.
2. The electronic package of claim 1 , wherein the capacitor dielectric layer is a high-k dielectric layer.
3. The electronic package of claim 2 , wherein the capacitor dielectric layer has a k-value that is 10 or greater.
4. The electronic package of claim 2 , wherein the capacitor dielectric layer has a k-value that is 100 or greater.
5. The electronic package of claim 1 , wherein the capacitor dielectric layer has a thickness that is less than 2 μm.
6. The electronic package of claim 1 , wherein the capacitor dielectric layer has a thickness that is less than 50 nm.
7. The electronic package of claim 1 , wherein the capacitor further comprises a first intermediate metal layer between the first electrode and the capacitor dielectric layer, and a second intermediate metal layer between the capacitor dielectric layer and the second electrode.
8. The electronic package of claim 7 , wherein the capacitor dielectric layer is TiO 2 , and wherein the first and second intermediate metal layers comprise titanium.
9. The electronic package of claim 8 , wherein the first and second intermediate metal layers comprise titanium and nitrogen.
10. The electronic package of claim 1 , wherein the capacitor further comprises a second capacitor dielectric over the second electrode, and a third electrode over the second capacitor dielectric, wherein the second capacitor dielectric is an amorphous dielectric layer.
11. The electronic package of claim 10 , wherein the capacitor has a thickness that is less than 10 μm.
12. The electronic package of claim 10 , wherein the capacitor is disposed entirely within a second dielectric layer formed over the first dielectric layer.
13. An electronics system comprising:
a package substrate;
a die electrically and mechanically coupled to the package substrate; and
a plurality of capacitors in the package substrate, wherein each of the plurality of capacitors comprises an amorphous dielectric layer.
14. The electronics system of claim 13 , wherein one or more of the plurality of capacitors are formed in a build-up layer of the package substrate closest to the die.
15. The electronics system of claim 13 , wherein the plurality of capacitors are formed in more than one build-up layer of the package substrate.
16. The electronics system of claim 13 , wherein the package substrate comprises a core, and first build-up layers over a first surface of the core, and second build-up layers over a second surface of the core.
17. The electronics system of claim 16 , wherein the plurality of capacitors are formed in the first build-up layers, wherein the first build-up layers are closer to the die than the second build-up layers.
18. The electronics system of claim 16 , wherein the plurality of capacitors are formed in the first build-up layers and the second build-up layers.
19. The electronics system of claim 13 , wherein each of the plurality of capacitors are disposed in a single build-up layer of the package substrate.
20. The electronics system of claim 13 , wherein the dielectric layer of each of the plurality of capacitors has a k-value greater than 10.
21. The electronics system of claim 13 , wherein one or more of the plurality of capacitors comprises a first amorphous dielectric layer and a second amorphous dielectric layer.
22. A method of forming a capacitor in a build-up layer, comprising:
disposing a first electrode on a first dielectric layer;
disposing an amorphous dielectric layer over the first electrode, wherein the amorphous dielectric layer has a thickness that is less than 50 nm and a k-value that is 10 or greater;
disposing a second electrode over the amorphous dielectric layer, wherein the first electrode and the second electrode comprise interdigitated portions; and
disposing a second dielectric layer over the first dielectric layer.
23. The method of claim 22 , further comprising:
disposing a first intermediate metal between the first electrode and the amorphous dielectric layer; and
disposing a second intermediate metal between the amorphous dielectric layer and the second electrode.
24. The method of claim 23 , wherein the amorphous dielectric layer is TiO 2 , and wherein the first and second intermediate metals comprise titanium.
25. An electronic package, comprising:
a dielectric layer; and
a capacitor on the dielectric layer, wherein the capacitor comprises:
a first electrode disposed over the dielectric layer;
a capacitor dielectric layer over the first electrode, wherein the capacitor dielectric layer is an amorphous dielectric layer; and
a second electrode over the capacitor dielectric layer, wherein the capacitor further comprises a second capacitor dielectric over the second electrode, and a third electrode over the second capacitor dielectric, wherein the second capacitor dielectric is an amorphous dielectric layer.