Integrated circuits
One of integrated circuits includes a substrate, a through via, a conductive pad and at least one via. The through via is disposed in the substrate. The conductive pad is disposed over and electrically connected to the through via, and the conductive pad includes at least one dielectric pattern therein. The via is disposed between and electrically connected to the through via and the conductive pad.
1. An integrated circuit, comprising:
a substrate;
a through via in the substrate;
a conductive pad, disposed over and electrically connected to the through via, the conductive pad comprising at least one dielectric pattern therein, wherein the at least one dielectric pattern penetrates a surface of the conductive pad; and
at least one via, disposed between and electrically connected to the through via and the conductive pad.
2. The integrated circuit according to claim 1 , wherein the conductive pad has a region, a projection of the region onto the substrate is entirely overlapped with a projection of the through via onto the substrate, and the at least one dielectric pattern is disposed within the region.
3. The integrated circuit according to claim 2 , wherein a conductor content of a portion of the conductive pad within the region is in a range of about 40% to about 80%.
4. The integrated circuit according to claim 2 , wherein the at least one dielectric pattern comprises a plurality of dielectric patterns, and the plurality of dielectric patterns are arranged along a periphery of the region.
5. The integrated circuit according to claim 1 , wherein the at least one dielectric pattern comprises a plurality of dielectric patterns, and from a top view, the plurality of dielectric patterns surround the at least one via.
6. The integrated circuit according to claim 1 , wherein the at least one dielectric pattern comprises a plurality of dielectric patterns, and each of the plurality of dielectric patterns penetrates the surface of the conductive pad.
7. The integrated circuit according to claim 1 further comprising an etch stop layer over the conductive pad, wherein the at least one dielectric pattern is integrally formed with the etch stop layer.
8. The integrated circuit according to claim 1 further comprising an etch stop layer and a dielectric layer sequentially over the conductive pad, wherein the at least one dielectric pattern is integrally formed with the etch stop layer and the dielectric layer.
9. An integrated circuit, comprising:
a substrate;
a through via in the substrate;
a conductive pad, disposed over and electrically connected to the through via, the conductive pad comprising a conductive main body and a plurality of holes in the conductive main body, wherein at least one of the plurality of holes penetrates a surface of the conductive main body; and
at least one via, disposed between and electrically connected to the through via and the conductive pad, wherein the plurality of holes surround the at least one via.
10. The integrated circuit according to claim 9 , wherein bottoms of the plurality of holes are substantially flush with a bottom of the conductive main body.
11. The integrated circuit according to claim 9 , wherein each of the plurality of holes penetrates through the conductive main body.
12. The integrated circuit according to claim 9 , wherein a height of the plurality of holes is smaller than a largest height of the conductive main body.
13. The integrated circuit according to claim 9 further comprising a dielectric layer over the conductive pad, wherein the at least one of the plurality of holes is partially filled by the dielectric layer.
14. The integrated circuit according to claim 9 , wherein the conductive pad further comprises a plurality of dielectric patterns above the plurality of holes respectively.
15. An integrated circuit, comprising:
a substrate;
a through via in the substrate; and
a conductive pad in an etch stop layer and a dielectric layer on the etch stop layer, the conductive pad electrically connected to the through via, the conductive pad comprising a conductive main body, a first dielectric pattern and a second dielectric pattern on the first dielectric pattern, wherein a material of a first dielectric pattern is the same as a material of the etch stop layer, and a material of a second dielectric pattern is different from the material of the first dielectric pattern and the same as a material of the dielectric layer.
16. The integrated circuit according to claim 15 , wherein a top surface of the first dielectric pattern is substantially flush with a top surface of the etch stop layer.
17. The integrated circuit according to claim 15 , wherein a top surface of the second dielectric pattern is substantially flush with a top surface of the dielectric layer.
18. The integrated circuit according to claim 15 , wherein a top surface of the second dielectric pattern is substantially flush with a top surface of the conductive main body.
19. The integrated circuit according to claim 15 , wherein a sidewall of the first dielectric pattern is substantially flush with a sidewall of the second dielectric pattern.
20. The integrated circuit according to claim 1 , wherein a surface of the at least one dielectric pattern is coplanar with the surface of the conductive pad.