Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices
A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.
1. A multi-pin wafer level chip scale package comprising:
one or more solder pillars and one or more solder blocks on a silicon wafer wherein said one or more solder pillars and said one or more solder blocks all have a top surface in a same horizontal plane and wherein at least one side of said solder blocks in a two-dimensional plane is greater than 600 μm and wherein said solder pillars are thinner and narrower than said solder blocks;
a pillar metal layer directly underlying each of said one or more solder pillars and electrically connecting said one or more solder pillars with said silicon wafer through an opening in a polymer layer over a passivation layer on said silicon wafer, wherein said pillar metal layer comprises:
a redistribution layer (RDL) trace contacting said silicon wafer at a silicon pad exposed by said opening in said polymer layer over said passivation layer; and
a block metal layer directly underlying each of said one or more solder blocks and electrically connecting said one or more solder blocks with said silicon wafer through a plurality of via openings through said polymer layer over said passivation layer on said silicon wafer, wherein said block metal layer comprises:
a redistribution layer via (RDL_VIA) contacting said silicon wafer through said plurality of via openings in said polymer layer and said passivation layer to said silicon wafer; and
an under block metal (UBM) layer covering said RDL_VIA layer in said plurality of via openings wherein said block metal layer is thicker and wider than said pillar metal layer wherein said RDL trace has a thickness of at least 4 μm, said RDL_VIA layer has a thickness of at least 25 μm, said UBM layer has a thickness of at least 25 μm and a width of at least 600 μm in at least one direction, said solder pillar has a height of at least 120 μm and said solder block has a height of at least 100 μm and a width of at least 600 μm.
2. A multi-pin wafer level chip scale package comprising:
one or more solder pillars and one or more solder blocks on a silicon wafer wherein said one or more solder pillars and said one or more solder blocks all have a top surface in a same horizontal plane and wherein at least one side of said solder blocks in a two-dimensional plane is greater than 600 μm and wherein said solder pillars are thinner and narrower than said solder blocks;
a pillar metal layer directly underlying each of said one or more solder pillars and electrically connecting said one or more solder pillars with said silicon wafer through an opening in a polymer layer over a passivation layer on said silicon wafer, wherein said pillar metal layer comprises:
an under pillar metal (UPM) trace contacting said silicon wafer at a silicon pad exposed by said opening in said polymer layer over said passivation layer; and
a block metal layer directly underlying each of said one or more solder blocks and electrically connecting said one or more solder blocks with said silicon wafer through a plurality of via openings through said polymer layer over said passivation layer on said silicon wafer, wherein said block metal layer comprises:
an under block metal layer (UBM) contacting said silicon wafer through said plurality of via openings in said polymer layer and said passivation layer to said silicon wafer and having a thickness overlying said plurality of via openings wherein said UPM trace has a thickness of at least 8 μm and at most 25 μm, said UBM layer has a thickness of at least 25 μm and a width of at least 600 μm in at least one direction, said solder pillar has a height of at least 120 μm and said solder block has a height of at least 100 μm and a width of at least 600 μm.
3. The multi-pin wafer level chip scale package according to claim 2 wherein said pillar metal layer further comprises:
a redistribution layer (RDL) trace contacting said silicon wafer at said silicon pad exposed by said opening in said polymer layer over said passivation layer; and
said under pillar metal (UPM) trace on said RDL trace.
4. The multi-pin wafer level chip scale package according to claim 2 wherein said block metal layer further comprises:
a redistribution layer via (RDL_VIA) contacting said silicon wafer through said plurality of via openings in said polymer layer and said passivation layer to said silicon wafer; and
said under block metal (UBM) layer covering said RDL_VIA layer in said plurality of via openings.
5. The multi-pin wafer level chip scale package according to claim 3 wherein said RDL trace has a thickness of at least 4 μm.
6. The multi-pin wafer level chip scale package according to claim 4 wherein said RDL_VIA layer has a thickness of at least 25 μm.