Methods for forming three-dimensional memeory devices with drain-select-gate cut structures
Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack comprising a plurality of first/second dielectric layer pairs over a substrate;
forming a drain-select-gate (DSG) cut opening in a core region of the dielectric stack;
forming a staircase structure comprising a plurality of stairs extending along a lateral direction in a staircase region of the dielectric stack;
forming, in a different process than the DSG cut opening, a second DSG cut opening in the staircase region and extending along the lateral direction;
depositing a dielectric material to respectively fill up the DSG cut opening and the second DSG cut opening; and
forming a DSG cut structure in the DSG cut opening and a second DSG cut structure in the second DSG cut opening, wherein the DSG cut structure and the second DSG cut structure are each a dielectric structure.
2. The method of claim 1 , further comprising:
forming, in a same process that forms the second DSG cut opening, a plurality of support openings extending along a vertical direction in the staircase region and being at least partially overlapped with the second DSG cut opening; and
forming a plurality of support structures in the plurality of support openings.
3. The method of claim 2 , wherein forming the plurality of support structures comprises depositing the dielectric material respectively in the plurality of support openings.
4. The method of claim 3 , wherein the dielectric material is deposited in a same process to form the DSG cut structure, the second DSG cut structure, and the plurality of support structures.
5. The method of claim 2 , wherein forming the plurality of support openings comprises removing a plurality of portions of the dielectric stack to expose the substrate.
6. The method of claim 1 , further comprising:
forming, in a different process that forms the second DSG cut opening, a plurality of support openings extending along a vertical direction in the staircase region; and
forming a plurality of support structures in the plurality of support openings.
7. The method of claim 1 , wherein the DSG cut opening is formed before a formation of the staircase structure.
8. The method of claim 1 , wherein forming the second DSG cut opening comprises removing a portion of the dielectric stack that comprises at least four first/second dielectric layer pairs.
9. The method of claim 8 , wherein forming the second DSG cut opening comprises removing a portion of the dielectric stack to expose the substrate.
10. The method of claim 1 , wherein the second DSG cut opening is formed after a formation of the staircase structure.
11. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack comprising a plurality of first/second dielectric layer pairs over a substrate;
forming a pair of slit structures extending along a lateral direction in the dielectric stack;
forming a drain-select-gate (DSG) cut opening between and parallel to the slit structures in a core region of the dielectric stack;
forming a staircase structure comprising a plurality of stairs extending along the lateral direction in a staircase region of the dielectric stack;
forming, in a different process than the DSG cut opening, a second DSG cut opening between and parallel to the slit structures in the staircase region of the dielectric stack; and
forming a DSG cut structure in the DSG cut opening and a second DSG cut structure in the second DSG cut opening.
12. The method of claim 11 , further comprising forming a plurality of channel structures in the core region, wherein a length of each of the DSG cut opening and the second DSG cut opening is greater than a length of at least two channel structures in the lateral direction.
13. The method of claim 11 , wherein the second DSG cut opening is formed after a formation of the staircase structure.
14. The method of claim 13 , wherein the DSG cut opening is formed after the formation of the staircase structure.
15. The method of claim 11 , wherein the DSG cut opening is formed before a formation of the staircase structure.
16. The method of claim 11 , further comprising:
forming, in a same process that forms the second DSG cut opening, a plurality of support openings extending along a vertical direction in the staircase region and being at least partially overlapped with the second DSG cut opening; and
forming a plurality of support structures in the plurality of support openings.
17. The method of claim 16 , wherein forming the DSG cut structure, the second DSG cut structure, and the plurality of support structures comprise depositing a dielectric material respectively in the DSG cut opening, the second DSG cut opening, and the plurality of support openings.
18. The method of claim 11 , further comprising:
forming, in a different process that forms the second DSG cut opening, a plurality of support openings extending along a vertical direction in the staircase region; and
forming a plurality of support structures in the plurality of support openings.
19. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack comprising a plurality of first/second dielectric layer pairs over a substrate;
forming a drain-select-gate (DSG) cut opening extending in a lateral direction in a core region of the dielectric stack;
forming a plurality of channel holes aligned and overlapped with the DSG cut opening in the core region in the lateral direction;
forming a staircase structure comprising a plurality of stairs extending along a lateral direction in a staircase region of the dielectric stack;
forming, in a different process than the DSG cut opening, a second DSG cut opening in the staircase region aligned with the DSG cut opening;
forming a plurality of dummy channel structures in the plurality of channel holes; and
forming a DSG cut structure in the DSG cut opening and a second DSG cut structure in the second DSG cut opening.
20. The method of claim 19 , wherein the second DSG cut opening is formed after a formation of the staircase structure.