Seal material for air gaps in semiconductor devices
The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.
1. A semiconductor device, comprising:
first and second terminals formed on a fin region;
a self-aligned contact (SAC) formed on the first terminal, wherein the SAC comprises a first silicon carbide material doped with oxygen;
a seal layer formed between the first and second terminals, wherein the seal layer comprises a second silicon carbide material doped with oxygen;
a spacer on the first terminal and on the fin region;
a contact etch stop layer (CESL) on the second terminal; and
an air gap surrounded by the seal layer, the spacer, and the CESL.
2. The semiconductor device of claim 1 , wherein the first terminal comprises a gate electrode and the second terminal comprises a source/drain (S/D) contact.
3. The semiconductor device of claim 2 , wherein:
the first terminal further comprises a gate dielectric layer on a sidewall of the gate electrode; and
the spacer comprises a first portion on a sidewall of the gate dielectric layer and a second portion on a top surface of the fin region.
4. The semiconductor device of claim 3 , wherein the air gap is in contact with the first and second portions of the spacer.
5. The semiconductor device of claim 1 , wherein an oxygen atomic content of the seal layer is between about 30% and about 55%.
6. The semiconductor device of claim 1 , wherein a carbon atomic content of the seal layer is between about 10% and about 35%.
7. The semiconductor device of claim 1 , wherein a silicon atomic content of the seal layer is between about 25% and about 35%.
8. The semiconductor device of claim 1 , wherein top surfaces of the seal layer, the first terminal, and the second terminal are substantially coplanar.
9. The semiconductor device of claim 1 , Wherein the SAC has a top surface that is substantially coplanar with a top surface of the seal layer.
10. The semiconductor device of claim 1 , Wherein the seal layer is formed on a sidewall of the spacer.
11. A semiconductor device, comprising:
a gate structure on a fin region, comprising:
a gate electrode; and
a self-aligned contact (SAC) formed on the gate electrode, wherein the SAC comprises a first silicon carbide material doped with oxygen;
a spacer in contact with the gate structure;
a source/drain (S/D) contact;
a contact etch stop layer (CESL) in contact with the S/D contact;
a seal layer comprising a second silicon carbide material doped with oxygen, wherein the seal layer further comprises:
a first portion between the gate structure and the S/D contact; and
a second portion on top surfaces of the SAC and the S/D contact; and
an air gap surrounded by the seal layer, the spacer, and the CESL.
12. The semiconductor device of claim 11 , wherein a density of the seal layer is between about 2.0 g/cm 3 and about 3.2 g/cm 3 .
13. The semiconductor device of claim 11 , wherein an oxygen atomic content of the seal layer is between about 30% and about 55%.
14. The semiconductor device of claim 11 , further comprising a via extending through the second portion of the seal layer and in contact with the SAC.
15. The semiconductor device of claim 11 , wherein the spacer comprises a first portion on a sidewall of a gate dielectric layer and a second portion on a top surface of the fin region.
16. A method for forming a semiconductor device, comprising:
forming an opening over a top surface of a substrate and between first and second terminals of the semiconductor device;
depositing a silicon carbide material in the opening and between the first and second terminals, wherein a pocket of air is entrapped in the opening surrounded by the silicon carbide material, the first and second terminals, and the substrate;
performing an oxygen anneal process on the silicon carbide material; and
depositing a dielectric layer on a top surface of the silicon carbide material and top surfaces of the first and second terminals.
17. The method of claim 16 , wherein the silicon carbide material is deposited at a top portion of the opening.
18. The method of claim 16 , wherein depositing the silicon carbide material comprises flowing tetramethyldisiloxane (TSMDSO), hydrogen gas, and oxygen gas into a deposition chamber.
19. The method of claim 18 , wherein a flow ratio of the hydrogen gas to the oxygen gas is between about 20 and about 30.
20. The method of claim 16 , further comprising:
etching the first terminal to recess the first terminal;
depositing another silicon carbide material on the recessed first terminal; and
performing another oxygen anneal process on the another silicon carbide material.