Independent control of stacked semiconductor device

1. A semiconductor device, comprising:

a first plurality of channel regions;

an isolation structure in contact with a top surface of the first plurality of channel regions;

a substrate layer in contact with the isolation structure;

an epitaxial layer in contact with the isolation structure and the substrate layer; and

a second plurality of channel regions above the first plurality of channel regions, wherein the epitaxial layer is between the isolation structure and the second plurality of channel regions.

2. The semiconductor device of claim 1 , further comprising a gate structure around the first and second plurality of channel regions.

3. The semiconductor device of claim 1 , further comprising:

a first gate structure around the first plurality of channel regions having a first gate length; and

a second gate structure around the second plurality of channel regions having a second gate length different from the first gate length.

4. The semiconductor device of claim 1 , wherein the first plurality of channel regions are along a first direction, and the second plurality of channel regions are along a second direction parallel to the first direction.

5. The semiconductor device of claim 1 , wherein the first plurality of channel regions comprise a first stack of semiconductor layers, and the second plurality of channel regions comprise a second stack of semiconductor layers.

6. The semiconductor device of claim 5 , wherein each layer of the first stack of semiconductor layers has a first thickness and each layer of the second stack of semiconductor layers has a second thickness different from the first thickness.

7. The semiconductor device of claim 5 , wherein each layer of the first stack of semiconductor layers has a first width and each layer of the second stack of semiconductor layers has a second width different from the first width.

8. The semiconductor device of claim 5 , wherein the first stack of semiconductor layers has a first spacing between each semiconductor layer and the second stack of semiconductor layers has a second spacing between each semiconductor layer, the second spacing being different from the first spacing.

9. The semiconductor device of claim 1 , wherein the isolation structure comprises silicon oxide.

10. A semiconductor device, comprising:

a first plurality of channel regions;

a first isolation structure on a top surface of the first plurality of channel regions;

a substrate layer on the first isolation structure;

a first epitaxial layer on the first isolation structure and the substrate layer;

a second isolation structure on the first epitaxial layer;

a second epitaxial layer on the second isolation structure, wherein the first epitaxial layer is between the first isolation structure and the second isolation structure; and

a second plurality of channel regions above the first plurality of channel regions.

11. The semiconductor device of claim 10 , further comprising:

a first gate structure around the first plurality of channel regions having a first gate length; and

a second gate structure around the second plurality of channel regions having a second gate length different from the first gate length.

12. The semiconductor device of claim 10 , wherein the first plurality of channel regions comprise a first stack of semiconductor layers and the second plurality of channel regions comprise a second stack of semiconductor layers.

13. The semiconductor device of claim 12 , wherein each layer of the first stack of semiconductor layers has a first thickness and each layer of the second stack of semiconductor layers has a second thickness different from the first thickness.

14. The semiconductor device of claim 12 , wherein each layer of the first stack of semiconductor layers has a first width and each layer of the second stack of semiconductor layers has a second width different from the first width.

15. The semiconductor device of claim 12 , wherein the first stack of semiconductor layers has a first spacing between each semiconductor layer and the second stack of semiconductor layers has a second spacing between each semiconductor layer, the second spacing being different from the first spacing.

16. The semiconductor device of claim 10 , wherein the first plurality of channel regions are along a first direction, and the second plurality of channel regions are along a second direction parallel to the first direction.

17. A semiconductor device, comprising:

a first plurality of channel regions including a first stack of semiconductor layers and epitaxial regions, wherein the epitaxial regions are in contact with the first stack of semiconductor layers;

an isolation structure in contact with the first stack of semiconductor layers and the epitaxial regions;

a substrate layer in contact with the isolation structure;

an epitaxial layer in contact with the isolation structure and the substrate layer; and

a second plurality of channel regions above the first plurality of channel regions, wherein the second plurality of channel regions includes a second stack of semiconductor layers and the epitaxial layer is between the isolation structure and the second plurality of channel regions.

18. The semiconductor device of claim 17 , wherein each layer of the first stack of semiconductor layers has a first thickness and each layer of the second stack of semiconductor layers has a second thickness different from the first thickness.

19. The semiconductor device of claim 17 , wherein each layer of the first stack of semiconductor layers has a first width and each layer of the second stack of semiconductor layers has a second width different from the first width.

20. The semiconductor device of claim 17 , wherein the substrate layer comprises a doping layer and a semiconductor layer.