Distance estimation using signals of different frequencies

1. A method implemented by a first device, the method comprising:

synchronizing a first signal generated from a signal generator with a local clock of the first device at a first time, the first signal having a first frequency;

sending the first signal to a second device;

synchronizing a second signal generated from the signal generator with the local clock of the first device at a second time, the second signal having a second frequency different from the first frequency, and a difference between the second time and the first time being within a predetermined range of a predetermined time difference; and

sending the second signal to the second device;

synchronizing a third signal and a fourth signal generated from the signal generator with the local clock at a third time and a fourth time respectively, the third signal having a third frequency and the fourth signal having a fourth frequency; and

sending the third signal and the fourth signal to the second device, wherein sending the first signal, the second signal, the third signal, and the fourth signal to the second device enables the second device to obtain a first estimated value for a distance between the first device and the second device based on a first phase difference between the first signal and the second signal, to obtain a second estimated value for the distance between the first device and the second device based on a second phase difference between the third signal and the fourth signal, and to obtain a final estimated value for the distance between the first device and the second device based on the first estimated value and the second estimated value.

2. The method of claim 1 , further comprising sending information of the first frequency, the second frequency and the predetermined time difference to the second device.

3. The method of claim 1 , wherein the signal generator comprises a fractional-N phase lock loop with a resetting circuit.

4. The method of claim 3 , wherein synchronizing the first signal generated from the signal generator with the local clock of the first device at the first time comprises performing a reset on the fractional-N phase lock loop through the resetting circuit at the first time.

5. The method of claim 1 , wherein synchronizing the first signal generated from the signal generator with the local clock of the first device comprises establishing a phase relationship between a phase of the first signal and the local clock.

6. One or more processor readable media storing executable instructions that, when executed by one or more processors of a first device, cause the one or more processors to perform acts comprising:

changing a signal frequency of a signal generator to a first frequency;

synchronizing signals generated from the signal generator with a local clock of the first device at a first time;

receiving a first signal from a second device;

changing the signal frequency of the signal generator to a second frequency;

synchronizing the signals generated from the signal generator with the local clock of the first device at a second time, a difference between the second time and the first time being within a predetermined range of a predetermined time difference;

receiving a second signal from the second device;

obtaining a first estimated value for a distance between the first device and the second device based on a first phase difference between the first signal and the second signal;

changing the signal frequency of the signal generator to a third frequency;

synchronizing the signals generated from the signal generator with the local clock of the first device at a third time;

receiving a third signal from the second device;

changing the signal frequency of the signal generator to a fourth frequency;

synchronizing the signals generated from the signal generator with the local clock of the first device at a fourth time;

receiving a fourth signal from the second device;

obtaining a second estimated value for the distance between the first device and the second device based on a second phase difference between the third signal and the fourth signal; and

obtaining a final estimated value for the distance between the first device and the second device based on the first estimated value and the second estimated value.

7. The one or more processor readable media of claim 6 , the acts further comprising receiving information of the first frequency, the second frequency and the predetermined time difference from the second device.

8. The one or more processor readable media of claim 6 , wherein the signal generator comprises a fractional-N phase lock loop with a resetting circuit.

9. The one or more processor readable media of claim 8 , wherein synchronizing the signals generated from the signal generator with the local clock of the first device at the first time comprises performing a reset on the fractional-N phase lock loop through the resetting circuit at the first time.

10. The one or more processor readable media of claim 6 , the acts further comprising calculating the predetermined range based at least in part on a frequency of the local clock and a fractional value.

11. The one or more processor readable media of claim 6 , wherein synchronizing the signals generated from the signal generator with the local clock of the first device comprises establishing a phase relationship between a phase of the signals and the local clock.

12. The one or more processor readable media of claim 6 , the acts further comprising:

calculating a clock frequency offset between the local clock of the first device and a local clock of the second device; and

correcting the calculated distance based at least in part on the calculated clock frequency offset.

13. A system implemented by a first processor chipset, the system comprising:

one or more processors; and

memory storing executable instructions that, when executed by the one or more processors, cause the one or more processors to perform acts comprising:

changing a signal frequency of a signal generator to a first frequency;

synchronizing signals generated from the signal generator with a local clock of the processor chipset at a first time;

receiving a first signal from a second processor chipset;

changing the signal frequency of the signal generator to a second frequency;

synchronizing the signals generated from the signal generator with the local clock of the first processor chipset at a second time, a difference between the second time and the first time being within a predetermined range of a predetermined time difference;

receiving a second signal from the second processor chipset;

calculating a distance between the first processor chipset and the second processor chipset based on a phase difference between the first signal and the second signal;

changing the signal frequency of the signal generator to a third frequency;

synchronizing the signals generated from the signal generator with the local clock of the first processor chipset at a third time;

receiving a third signal from the second device;

changing the signal frequency of the signal generator to a fourth frequency;

synchronizing the signals generated from the signal generator with the local clock of the first processor chipset at a fourth time;

receiving a fourth signal from the second device;

obtaining a second estimated value for the distance between the first processor chipset and the second processor chipset based on a second phase difference between the third signal and the fourth signal; and

obtaining a final estimated value for the distance between the first device and the second device based on the first estimated value and the second estimated value.

14. The system of claim 13 , the acts further comprising receiving information of the first frequency, the second frequency and the predetermined time difference from the second processor chipset.

15. The system of claim 13 , wherein the signal generator comprises a fractional-N phase lock loop with a resetting circuit.

16. The system of claim 15 , wherein synchronizing the signals generated from the signal generator with the local clock of the first processor chipset at the first time comprises performing a reset on the fractional-N phase lock loop through the resetting circuit at the first time.

17. The system of claim 13 , the acts further comprising:

calculating a clock frequency offset between the local clock of the first processor chipset and a local clock of the second processor chipset; and

correcting the calculated distance based at least in part on the calculated clock frequency offset.