IP Library › Granted Patent US 11,507,290
Granted Patent B2
US 11,507,290 · App. 16/830,386 · Granted Nov 22, 2022

Method and apparatus for storage device management

Inventors: Nickolay Dalmatov (St. Petersburg, RU); Assaf Natanzon (Tel Aviv, IL)
Assignee: EMC IP Holding Company LLC
G06F3/064G06F3/0611G06F3/0658G06F3/0688G06F11/3034G06F12/1009G06N20/00G06F2212/7201
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Quick Facts
Patent No.
US 11,507,290
App. No.
16/830,386
Granted
Nov 22, 2022
Kind
B2
Abstract

A method for provided use in a storage device having a controller, the method comprising: identifying, by the controller, a plurality of logical regions in the storage device; obtaining, by the controller, a respective usage metric for each of the logical regions; updating, by the controller, a translation data structure of the storage device, the translation data structure being updated to map any of the logical regions of the storage device to a respective physical portion of the storage device, the respective physical portion being selected based on the respective usage metric of the logical region, wherein the translation data structure is part of a flash translation layer of the storage device, and the translation data structure is configured to store mapping information between a logical address space of the storage device and a physical address space of the storage device.

Claims (34)

1. A method for use in a storage device having a controller, the method comprising:

identifying, by the controller, a plurality of logical regions in the storage device; and

updating, by the controller, a translation data structure of the storage device, the translation data structure being updated by: calculating a respective predicted load of each of the logical regions by executing a machine learning engine, grouping the logical regions into a plurality of groups based on the predicted loads, and mapping each of the group to a corresponding memory block of the storage device, the corresponding memory block being selected based on a wear level of the corresponding memory block and the predicted loads of the logical regions in the group,

wherein the translation data structure is part of a flash translation layer of the storage device,

wherein the translation data structure is configured to store mapping information between a logical address space of the storage device and a physical address space of the storage device, and

wherein the machine learning engine is executed in the flash translation layer of the storage device, the flash translation layer including an interface that is configured to provide logical-to-physical address mapping for the storage device.

2. The method of claim 1 , wherein grouping the logical regions based on the predicted loads causes a distance to be minimized, in any of the groups, between a predicted load of a logical region that has the smallest predicted load in the group and a predicted load of another logical region that has the largest predicted load in the group.

3. The method of claim 1 , wherein each of the groups to a respective memory block of the storage device includes assigning each of the groups to a respective contiguous physical portion of the storage device.

4. The method of claim 1 , wherein each of the logical regions includes a page.

5. The method of claim 1 , wherein the predicted load of any of the plurality of logical regions is based on at least one of (i) a count of write requests that are expected to be received during a future time window, (ii) a count of read requests that are expected to be received during the future time window, (iii) a rate at which write requests are expected to be received during the future time window, (iv) a rate at which read requests are expected to be received during the future time window, and (v) a read-to-write ratio that is expected to occur during the future time window.

6. The method of claim 1 , wherein the machine leering engine is trained based on training data, the training data including a read-to-write ratio of any of the logical regions.

7. A storage device, comprising:

a plurality of memory banks;

a processing circuitry operatively coupled to the memory banks, the processing circuitry being configured to perform the operations of:

identifying a plurality of logical regions in the storage device; and

updating a translation data structure of the storage device, the translation data structure being updated by: calculating a respective predicted load of each of the logical regions by executing a machine learning engine, grouping the logical regions into a plurality of groups based on the predicted loads, and mapping each of the groups to a corresponding memory block of the storage device, the corresponding memory block being selected based on a wear level of the corresponding memory block and the predicted loads of the logical regions in the group,

wherein the translation data structure is part of a flash translation layer of the storage device, and the translation data structure is configured to store mapping information between a logical address space of the storage device and a physical address space of the storage device, and

wherein the machine learning engine is executed in the flash translation layer of the storage device, the flash translation layer including an interface that is configured to provide logical-to-physical address mapping for the storage device.

8. The storage device of claim 7 , wherein grouping the logical regions based on the predicted loads causes a distance to be minimized, in any of the groups, between a predicted load of a logical region that has the smallest predicted load in the group and a predicted load of another logical region that has the largest predicted load in the group.

9. The storage device of claim 7 , wherein mapping each of the groups to a respective memory block of the storage device includes assigning each of the groups to a respective contiguous physical portion of the storage device.

10. The storage device of claim 7 , wherein each of the logical regions includes a page.

11. The storage device of claim 7 , wherein the predicted load of any of the plurality of logical regions is based on at least one of (i) a count of write requests that are expected to be received during a future time window, (ii) a count of read requests that are expected to be received during the future time window, (iii) a rate at which write requests are expected to be received during the future time window, (iv) a rate at which read requests are expected to be received during the future time window.

12. The storage device of claim 7 , wherein the machine learning engine is trained based on training data, the training data including a read-to-write ratio of any of the logical regions.

13. A non-transitory computer-readable medium storing one or more processor-executable instructions, which when executed by a controller of a storage device cause the controller to perform the operations of:

identifying a plurality of logical regions in the storage device; and

updating a translation data structure of the storage device, the translation data structure being updated by: calculating a respective predicted load of each of the logical regions by executing a machine learning engine, grouping the logical regions into a plurality of groups based on the predicted loads, and mapping each of the groups to a corresponding memory block of the storage device, the corresponding memory block being selected based on a wear level of the corresponding memory block and the predicted loads of the logical regions in the group,

wherein the translation data structure is part of a flash translation layer of the storage device, and

wherein the translation data structure is configured to store mapping information between a logical address space of the storage device and a physical address space of the storage device, and

wherein the machine learning engine is executed in the flash translation layer of the storage device, the flash translation layer including an interface that is configured to provide logical-to-physical address mapping for the storage device.

14. The non-transitory computer-readable medium of claim 13 , wherein grouping the logical regions based on the predicted loads causes a distance to be minimized, in any of the groups, between a predicted load of a logical region that has the smallest predicted load in the group and a predicted load of another logical region that has the largest predicted load in the group.

15. The non-transitory computer-readable medium of claim 13 , wherein mapping each of the groups to a respective memory block of the storage device includes assigning each of the groups to a respective contiguous physical portion of the storage device.

16. The non-transitory computer-readable medium of claim 13 , wherein each of the logical regions includes a page.

17. The non-transitory computer-readable medium of claim 13 , wherein the predicted load of any of the plurality of logical regions is based on at least one of (i) a count of write requests that are expected to be received during a future time window, (ii) a count of read requests that are expected to be received during the future time window, (iii) a rate at which write requests are expected to be received during the future time window, (iv) a rate at which read that is expected to occur during the future time window.

18. The non-transitory computer-readable medium of claim 13 , wherein the machine learning engine is trained based on training data, the training data including a read-to-write ratio of any of the logical regions.

Assignments (11)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0081) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0441 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052851/0917) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0509 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052852/0022) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060436/0582 →
RELEASE OF SECURITY INTEREST AT REEL 052771 FRAME 0906 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0298 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0081 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052852/0022 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052851/0917 →
SECURITY AGREEMENT Recorded May 28, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052771/0906 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2020
From: DALMATOV, NICKOLAY; NATANZON, ASSAF
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 052302/0540 →
Continuity (1)
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