Memory controller and storage device including the same

1. A memory controller, comprising:

a command storage including a first read command queue and a second read command queue, the first read command queue configured to store a read command and a physical address according to an index number, the read command to read data stored in a memory device and the physical address corresponding to the read command and including a plane number, a block number, and a page number;

a command generation controller configured to provide an erase command to perform an erase operation including erasing data stored in one of a plurality of memory blocks of the memory device, provide a suspend command to suspend the erase operation in response to a request, provide a resume command to resume the erase operation after an operation corresponding to the request is completed, and output a scheduling event signal after the resume command is output; and

a command schedule controller configured to, in response to the scheduling event signal:

search for a first physical address group including physical addresses having a same page number among physical addresses stored in the first read command queue and a second physical address group including all physical addresses having a plane number different from the plane number of the first physical address group, among the physical addresses stored in the first read command queue,

reorder an output sequence of the first read command queue by storing together the physical addresses of the first physical address group corresponding to the same page number at same index numbers of the second read command queue and storing respectively the physical addresses of the second physical address group at the index numbers of the second read command queue, and

provide the read command to perform a read operation based on the second read command queue.

2. The memory controller of claim 1 , wherein the first physical address group includes physical addresses having a same plane number, a same block number, and a same page number.

3. The memory controller of claim 2 , wherein the command schedule controller is configured to schedule the first physical address group and a read command corresponding to the first physical address group, in any one index number among index numbers of the second read command queue.

4. The memory controller of claim 1 , wherein the first physical address group includes physical addresses having different plane numbers and a same page number.

5. The memory controller of claim 4 , wherein the command schedule controller is configured to schedule the first physical address group and read commands corresponding to the first physical address, in any one index number among the index numbers of the second read command queue.

6. The memory controller of claim 1 , wherein, when the first physical address group is not searched, the command schedule controller is configured to:

search for a plane interleaving group including all physical addresses having different plane numbers, among the physical addresses stored in the first read command queue;

sequentially schedule physical addresses in the plane interleaving group in the consecutive index numbers of the second read command queue; and

sequentially schedule a read command corresponding to each physical address in the plane interleaving group in the consecutive index numbers.

7. The memory controller of claim 6 , wherein the command schedule controller is configured to:

sequentially schedule the physical addresses in the plane interleaving group, in index numbers from an index number corresponding to a first priority output sequence of the second read command queue; and

sequentially schedule the read command corresponding to each physical address in the plane interleaving group, in the index numbers from the index number corresponding to the first priority output sequence of the second read command queue.

8. A memory controller, comprising:

a command storage including a first read command queue and a second read command queue, the first read command queue configured to store a read command and a physical address according to an index number, the read command to read data stored in a memory device and the physical address corresponding to the read command and including a plane number, a block number, and a page number;

a command generation controller configured to provide the memory device with a command to perform an erase operation including erasing data stored in one memory block among a plurality of memory blocks of the memory device, or to perform a write operation including storing data in one memory block among the plurality of memory blocks, and to output a scheduling event signal after a predetermined period elapses from a time at which the command is provided to the memory device; and

a command schedule controller configured to, in response to the scheduling event signal:

search for a first physical address group including physical addresses having the same page number among physical addresses stored in the first read command queue and a second physical address group including all physical addresses having a plane number different from the plane number of the first physical address group, among the physical addresses stored in the first read command queue,

reorder an output sequence of the first read command queue by storing together the physical addresses of the first physical address group corresponding to the same page number at same index numbers of the second read command queue and storing respectively the physical addresses of the second physical address group at the index numbers of the second read command queue, and

provide the read command to perform a read operation based on the second read command queue.

9. The memory controller of claim 8 , wherein the first physical address group includes physical addresses having a same plane number, a same block number and a same page number.

10. The memory controller of claim 9 , wherein the command schedule controller is configured to schedule the first physical address group and a read command corresponding to the first physical address group, in any one index number among index numbers of the second read command queue.

11. The memory controller of claim 8 , wherein the first physical address group includes physical addresses having different plane numbers and a same page number.

12. The memory controller of claim 11 , wherein the command schedule controller is configured to schedule the first physical address group and read commands corresponding to the first physical address, in any one index number among the index numbers of the second read command queue.

13. The memory controller of claim 8 , wherein, when the first physical address group is not searched, the command schedule controller is configured to:

search for a plane interleaving group including all physical addresses having different plane numbers among the physical addresses stored in the first read command queue;

sequentially schedule physical addresses in the plane interleaving group in the consecutive index numbers of the second read command queue; and

sequentially schedule a read command corresponding to each physical address in the plane interleaving group in the consecutive index numbers.

14. The memory controller of claim 13 , wherein the command schedule controller is configured to:

sequentially schedule the physical addresses in the plane interleaving group in index numbers from an index number corresponding to a first priority output sequence of the second read command queue; and

sequentially schedule the read command corresponding to each physical address in the plane interleaving group in the index numbers from the index number corresponding to the first priority output sequence of the second read command queue.

15. A storage device, comprising:

a memory device including a plurality of planes; and

a memory controller configured to, in response to a read request:

store a read command and a physical address in a first read command queue according to an index number, the read command to perform a read operation including reading data stored in the memory device,

schedule read commands and physical addresses, which are stored in the first read command queue, in a second read command queue when a scheduling event occurs, and

provide the memory device with read commands and physical addresses, which are stored in the second read command queue, according to a scheduled sequence, wherein the physical address includes a plane number, a block number, and a page number, and

wherein the memory controller is configured to:

search for a first physical address group including physical addresses having a same page number among the physical addresses stored in the first read command queue and a second physical address group including all physical addresses having a plane number different from the plane number of the first physical address group, among the physical addresses stored in the first read command queue;

reorder an output sequence of the first read command queue by storing together the physical addresses of the first physical address group corresponding to the same page number at same index numbers of the second read command queue and storing respectively the physical addresses of the second physical address group at the index numbers of the second read command queue; and

provide the read command to perform a read operation based on the second read command queue.

16. The storage device of claim 15 , wherein:

the first physical address group includes physical addresses having a same plane number, a same block number and a same page number, and

the memory controller is configured to schedule the first physical address group and a read command corresponding to the first physical address group, in one index number among index numbers of the second read command queue.

17. The storage device of claim 16 , wherein, in response to the first physical address group and a read command corresponding to the first physical address group, the memory device is configured to:

perform a read operation on a page of a single plane having the physical addresses in the first physical address group, and

provide the memory controller with data stored in the page of the single plane.

18. The storage device of claim 15 , wherein:

the first physical address group includes physical addresses having different plane numbers and the same page number, and

the memory controller is configured to schedule the first physical address group and read commands corresponding to the first physical address, in one index number among the index numbers of the second read command queue.

19. The storage device of claim 18 , wherein, in response to the first physical address group and read commands corresponding to the first physical address group, the memory device is configured to:

simultaneously perform a read operation on pages of respective planes having the physical addresses in the first physical address group; and

provide the memory controller with data stored in pages of the respective planes.

20. The storage device of claim 15 , wherein the memory device is configured to:

perform a first read operation on a page of at least one plane having the physical addresses in the first physical address group, in response to the first physical address group and at least one read command corresponding to the first physical address group; and

perform a second read operation on a page of at least one plane having the physical addresses in the second physical address group, in response to the second physical address group and at least one read command corresponding to the second physical address group, wherein the first read operation and the second read operation are configured to partially overlap with each other.