Methods and apparatus to facilitate an atomic operation and/or a histogram operation in cache pipeline
Methods, apparatus, systems and articles of manufacture to facilitate an atomic operation and/or a histogram operation in cache pipeline are disclosed. An example system includes a cache storage coupled to an arithmetic component; and a cache controller coupled to the cache storage, wherein the cache controller is operable to: receive a memory operation that specifies a set of data; retrieve the set of data from the cache storage; utilize the arithmetic component to determine a set of counts of respective values in the set of data; generate a vector representing the set of counts; and provide the vector.
1. A system comprising:
a cache storage coupled to an arithmetic component; and
a cache controller coupled to the cache storage, wherein the cache controller is operable to:
receive instructions corresponding to a histogram operation that specifies a set of data;
retrieve the set of data from the cache storage;
utilize the arithmetic component to;
determine a set of counts of respective values in the set of data; and
perform the histogram operation by generating a vector representing the set of counts corresponding to respective values in the set of data to (a) initiate the vector including elements corresponding to the histogram operation and (b) update the vector by incrementing the set of counts based on the set of data; and
provide the vector.
2. The system of claim 1 , wherein the cache controller is operable to provide the vector for storing in the cache storage.
3. The system of claim 1 , wherein the cache controller is operable to provide the vector to a processor.
4. The system of claim 1 , further including store queue circuitry coupled to the cache controller, the store queue circuitry including the arithmetic component.
5. The system of claim 1 , wherein the cache storage is at least one of a main cache storage or a victim cache storage.
6. The system of claim 1 , wherein the arithmetic component is to obtain (a) the set of data from the cache storage via an error detection and correction circuit and (b) the histogram operation from a central processing unit via a latch.
7. The system of claim 1 , wherein the cache controller is operable to generate the vector and provide the vector to a central processing unit based on a single instruction from the central processing unit at a single cycle.
8. A system comprising:
a cache storage; and
a cache controller coupled to the cache storage and an arithmetic component, wherein the cache controller is operable to:
receive instructions corresponding to a histogram operation corresponding to a first set of data, the histogram operation corresponding to a histogram operation corresponding to the first set of data;
access the first set of data from the cache storage;
utilize the arithmetic component to;
determine a set of counts of respective values in the first set of data; and
perform the histogram operation by generating a second set of data representing the set of counts corresponding to respective values in the first set of data to (a) initiate the second set of data including elements corresponding to the histogram operation and (b) update the second set of data by incrementing the set of counts based on the first set of data; and
provide the second set of data.
9. The system of claim 8 , wherein the cache controller is operable to provide the second set of data for storing in the cache storage.
10. The system of claim 8 , wherein the cache controller is operable to provide the second set of data to a processor.
11. The system of claim 8 , further including store queue circuitry coupled to the cache controller, the store queue circuitry including the arithmetic component.
12. The system of claim 8 , wherein the cache storage is a victim cache storage.
13. The system of claim 8 , wherein the arithmetic component is to obtain (a) the first set of data from the cache storage via an error detection and correction circuit and (b) the instructions corresponding to the histogram operation from a central processing unit via a latch.
14. The system of claim 8 , wherein the cache controller is operable to product and provide the second set of data to a central processing unit based on a single instruction from the central processing unit at a single cycle.
15. A method comprising:
obtaining instructions corresponding to a histogram operation that specifies a set of data;
obtaining the set of data from a cache storage;
determining, by executing an instruction with a cache controller, a set of counts of respective values in the set of data;
performing by executing an instruction with the cache controller, the histogram operation by generating a vector representing the set of counts corresponding to respective values in the set of data to (a) initiate the vector including elements corresponding to the histogram operation and (b) update the vector by incrementing the set of counts based on the set of data; and
providing the vector.
16. The method of claim 15 , wherein the vector is provided to the cache storage.
17. The method of claim 15 , wherein the cache storage is a main cache storage.
18. The method of claim 15 , further including obtaining (a) the set of data from the cache storage via an error detection and correction circuit and (b) the histogram operation from a central processing unit via a latch.
19. The method of claim 15 , wherein the generating and providing of the vector to a central processing unit is performed in response to a single instruction from the central processing unit at a single cycle.
20. The method of claim 15 , wherein the cache storage is a victim cache storage.