Tracking streaming engine vector predicates to control processor execution
In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.
1. A circuit comprising:
a processor;
a memory circuit coupled to the processor and configured to couple to a memory, wherein the memory circuit includes:
an address generator configured to generate a set of addresses;
a memory interface coupled to the address generator and configured to retrieve a set of data elements associated with the set of addresses from the memory;
a head register coupled to the memory interface and to the processor and configured to:
store the set of data elements; and
provide a data stream that includes the set of data elements to the processor; and
a valid register coupled to the memory interface and to the processor and configured to:
store a set of valid indicators; and
provide a first valid indicator of the set of valid indicators to the processor, wherein the first valid indicator is associated with a first portion of the data stream and indicates whether the first portion is valid.
2. The circuit of claim 1 , wherein:
the head register includes a plurality of bytes grouped in lanes such that each lane stores one data element of the set of data elements; and
the valid register includes a plurality of bits associated with the plurality of bytes of the head register such that each bit of the plurality of bits of the valid register indicates whether one respective byte of the plurality of bytes of the head register is valid.
3. The circuit of claim 1 , wherein:
the head register includes a plurality of bytes grouped in lanes such that each lane stores one data element of the set of data elements;
the lanes have a minimum lane size; and
the valid register includes a plurality of bits associated with the lanes of the head register such that each bit of the plurality of bits of the valid register indicates whether a respective portion of the head register having the minimum lane size is valid.
4. The circuit of claim 1 , wherein:
the memory circuit further includes:
a first decoder configured to determine a size of each element of the set of data elements;
a second decoder configured to determine a promote factor for each element of the set of data elements; and
the memory circuit is configured to determine the set of valid indicators based on the size and the promote factor.
5. The circuit of claim 4 , wherein:
the head register includes a plurality of bytes grouped in lanes such that each lane stores one data element of the set of data elements;
the memory circuit further includes a multiplication circuit configured to determine a size of the lanes of the head register based on the size of each element of the set of data elements and the promote factor; and
the memory circuit is configured to determine the set of valid indicators based on the size of the lanes of the head register.
6. The circuit of claim 5 , wherein:
the memory circuit further includes a lane decoder configured to determine a number of lanes of the data stream based on the size of the lanes; and
the memory circuit is configured to determine the set of valid indicators based on the number of lanes of the data stream.
7. The circuit of claim 1 , wherein:
the address generator includes a set of loop counters;
the address generator is configured to generate the set of addresses based on the set of loop counters; and
the memory circuit is configured to determine the set of valid indicators based on the set of loop counters.
8. The circuit of claim 1 , wherein the memory circuit is further configured to:
receive a read instruction from the processor; and
in response to the read instruction:
provide the first portion of the data stream from the head register; and
provide the first valid indicator from the valid register.
9. The circuit of claim 1 further comprising the memory.
10. The circuit of claim 9 , wherein:
the memory is a level-two (L2) cache of a cache hierarchy; and
the memory interface is configured to retrieve the set of data elements from the L2 cache via a data path that does not include a level-one (L1) cache of the cache hierarchy.
11. The circuit of claim 1 further comprising:
a data storage coupled to the memory interface and configured to store the set of data elements; and
a butterfly network coupled between the data storage and the head register and configured to modify a bit order of the set of data elements prior to the head register storing the set of data elements.
12. A method comprising:
receiving a stream open instruction from a processor;
based on the stream open instruction, generating a set of addresses;
retrieving a set of data elements associated with the set of addresses from a memory;
storing the set of data elements in a head register;
storing a set of valid indicators in a valid register;
receiving a read instruction from the processor; and
based on the read instruction, providing a first portion of a data stream and a first valid indicator associated with the first portion of the data stream, wherein:
the data stream includes the set of data elements; and
the first valid indicator indicates whether the first portion of the data stream includes a data element of the set of data elements.
13. The method of claim 12 , wherein:
the head register includes a plurality of bytes grouped in lanes such that each lane stores one data element of the set of data elements; and
the valid register includes a plurality of bits associated with the plurality of bytes of the head register such that each bit of the plurality of bits of the valid register indicates whether one respective byte of the plurality of bytes of the head register contains a byte of a data element of the set of data elements.
14. The method of claim 12 , wherein:
the head register includes a plurality of bytes grouped in lanes such that each lane stores one data element of the set of data elements; and
the lanes have a minimum lane size; and
the valid register includes a plurality of bits associated with the lanes of the head register such that each bit of the plurality of bits of the valid register indicates whether a respective portion of the head register having the minimum lane size contains at least a portion of a data element of the set of data elements.
15. The method of claim 12 , wherein the storing of the set of valid indicators includes:
determining a size of each element of the set of data elements;
determining a promote factor for each element of the set of data elements; and
determining the set of valid indicators based on the size and the promote factor.
16. The method of claim 15 , wherein:
the head register includes a plurality of bytes grouped in lanes such that each lane stores one data element of the set of data elements; and
the storing of the set of valid indicators further includes:
determining a size of the lanes of the head register based on the size of each element of the set of data elements and the promote factor; and
determining the set of valid indicators based on the size of the lanes of the head register.
17. The method of claim 16 , wherein the storing of the set of valid indicators further includes:
determining a number of lanes of the data stream based on the size of the lanes; and
determining the set of valid indicators based on the number of lanes of the data stream.
18. The method of claim 12 , wherein:
the generating of the set of addresses is performed using a set of loop counters; and
the storing of the set of valid indicators includes determining the set of valid indicators based on the set of loop counters.
19. The method of claim 12 , wherein:
the memory is a level-two (L2) cache of a cache hierarchy; and
the retrieving of the set of data elements from the L2 cache is performed via a data path that does not include a level-one (L1) cache of the cache hierarchy.
20. The method of claim 12 , wherein the read instruction is a read and advance instruction.