Memory request priority assignment techniques for parallel processors
Systems, apparatuses, and methods for implementing memory request priority assignment techniques for parallel processors are disclosed. A system includes at least a parallel processor coupled to a memory subsystem, where the parallel processor includes at least a plurality of compute units for executing wavefronts in lock-step. The parallel processor assigns priorities to memory requests of wavefronts on a per-work-item basis by indexing into a first priority vector, with the index generated based on lane-specific information. If a given event is detected, a second priority vector is generated by applying a given priority promotion vector to the first priority vector. Then, for subsequent wavefronts, memory requests are assigned priorities by indexing into the second priority vector with lane-specific information. The use of priority vectors to assign priorities to memory requests helps to reduce the memory divergence problem experienced by different work-items of a wavefront.
1. A processor comprising:
a compute unit comprising a plurality of lanes configured to execute work-items of a wavefront in parallel; and
control logic configured to:
assign a first priority to each lane of a plurality of lanes of the compute unit based on a mapping of priorities to lanes;
assign a priority to a memory request of each work-item of the wavefront based on a priority of a corresponding lane;
execute work-items of the wavefront; and
responsive to detecting a first event, wherein the first event is completion of a last memory request of the wavefront:
assign a second priority to each lane of the plurality of lanes; and
assign a priority to a memory request of each work-item based on a priority of a corresponding lane.
2. The processor as recited in claim 1 , wherein the control logic is further configured to
generate a first mapping of priorities and assign the first priority to each lane based on the first mapping;
apply an update to the first mapping to generate a second mapping of priorities to lanes responsive to detecting the first event during execution of the wavefront; and
assign the second priority based on the second mapping.
3. The processor as recited in claim 1 , wherein the control logic is further configured to:
perform a lookup for each memory request based on static information and dynamic system state information to retrieve a priority; and
for each memory request, assign the retrieved priority to the memory request.
4. The processor as recited in claim 1 , wherein each separate type of event has a corresponding update to apply to a mapping of priorities to lanes which is different from updates of other types of events.
5. The processor as recited in claim 4 , wherein the control logic is further configured to apply an update to a mapping of priorities to lanes so as to minimize a memory divergence between different work-items of the wavefront.
6. The processor as recited in claim 4 , wherein each application executed by the processor has a separate mapping of priorities to lanes assigned to the application.
7. A method comprising:
assigning a first priority to each lane of a plurality of lanes of a compute unit based on a mapping of priorities to lanes;
assigning a priority to a memory request of each work-item of a wavefront based on a priority of a corresponding lane;
executing work-items of a wavefront;
processing, by a memory subsystem, each memory request according to a corresponding priority;
responsive to detecting a first event, wherein the first event is completion of a last memory request of the wavefront:
assigning a second priority to each lane of the plurality of lanes; and
assigning a priority to a memory request of each work-item based on a priority of a corresponding lane.
8. The method as recited in claim 7 , further comprising:
generating a first mapping of priorities and assigning the first priority to each lane based on the first mapping;
applying an update to the first mapping to generate a second mapping of priorities to lanes responsive to detecting the first event during execution of the wavefront and assigning the second priority based on the second mapping.
9. The method as recited in claim 7 , further comprising:
performing a lookup for each memory request based on static information and dynamic system state information to retrieve a priority; and
for each memory request, assigning the retrieved priority to the memory request.
10. The method as recited in claim 7 , wherein each separate type of event has a corresponding update to apply to a mapping of priorities to lanes which is different from priority promotion vectors of other types of events.
11. The method as recited in claim 10 , further comprising applying an update to a mapping of priorities to lanes so as to minimize a memory divergence between different work-items of the wavefront.
12. The method as recited in claim 10 , wherein each application has a separate mapping of priorities to lanes assigned to the application.
13. A system comprising:
a processor coupled to a memory subsystem, wherein the processor is configured to:
execute work-items of a wavefront in parallel, wherein each work-item executes on a corresponding lane of a plurality of lanes of a compute unit;
assign a first priority to each lane of the plurality of lanes of the compute unit;
assign a priority to a memory request of each work-item of the wavefront based on a priority of a corresponding lane;
assign a second priority to each lane of the plurality of lanes, responsive to detecting a first event during execution of the wavefront;
subsequent to the first event:
assign a second priority to each lane such that at least one lane has a changed priority;
assign a priority to a memory request of each work-item based on a priority of a corresponding lane; and
apply an update to a previously generated first mapping to generate a second mapping of priorities to lanes responsive to detecting the first event during execution of the wavefront.
14. The system as recited in claim 13 , wherein the first event is completion of a last memory request for a given instruction of the wavefront.
15. The system as recited in claim 13 , wherein the processor is further configured to:
perform a lookup for each memory request based on static information and dynamic system state information to retrieve a priority; and
for each memory request, assign the retrieved priority to the memory request.
16. The system as recited in claim 13 , wherein each separate type of event has a corresponding update to apply to a mapping of priorities to lanes which is different from updates of other types of events.
17. The system as recited in claim 16 , wherein the processor is further configured to apply an update to a mapping of priorities to lanes so as to minimize a memory divergence between different work-items of the wavefront.
18. A system comprising:
a processor coupled to a memory subsystem, wherein the processor is configured to:
execute work-items of a wavefront in parallel, wherein each work-item executes on a corresponding lane of a plurality of lanes of a compute unit;
assign a first priority to each lane of the plurality of lanes of the compute unit;
assign a priority to a memory request of each work-item of the wavefront based on a priority of a corresponding lane;
assign a second priority to each lane of the plurality of lanes, responsive to detecting a first event during execution of the wavefront, wherein the first event is completion of a last memory request for a given instruction of the wavefront,
subsequent to the first event:
assign a second priority to each lane such that at least one lane has a changed priority; and
assign a priority to a memory request of each work-item based on a priority of a corresponding lane.