RTOS/OS architecture for context switching that solves the diminishing bandwidth problem and the RTOS response time problem using unsorted ready lists
View Patent ↗The present invention is a novel RTOS/OS architecture that changes the fundamental way that context switching is performed. In all prior operating system implementations, context switching required disabling of interrupts. This opens the possibility that data can be lost. This novel approach consists of a context switching method in which interrupts are never disabled. Two implementations are presented. In the first implementation, the cost is a negligible amount of memory. In the second, the cost is only a minimal impact on the context switching time. This RTOS/OS architecture requires specialized hardware. Concretely, an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts is needed (e.g. the Nested Vectored Interrupt Controller (NVIC) found on many ARM processors). The novel RTOS/OS architecture redefines how task synchronization primitives such as semaphores and mutexes are released. Whereas previous architectures directly accessed internal structures, this architecture does so indirectly by saving information in shared buffers or setting flags, and then activating a low priority software interrupt that subsequently interprets this data and performs all context switching logic. The software interrupt must be set as the single lowest priority interrupt in the system.
1. A context switching method for real-time operating systems (RTOS), that execute on hardware with an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts, which never disables interrupts by handling semaphores released by hardware interrupt handlers in a low priority software interrupt, the method comprising:
Responsive to an interrupt occurring, releasing, by a hardware interrupt handler, a semaphore associated with the interrupt;
Storing, by the hardware interrupt handler, a reference to the semaphore in a circular buffer, wherein the storing comprises:
Reading a head of the circular buffer,
Storing the semaphore reference at the location of the head,
Incrementing the head of the circular buffer,
Responsive to the storing of the semaphore reference, activating a low priority software interrupt handler;
Reading, by the low priority software interrupt handler, from a tail of the circular buffer, the semaphore reference stored by the hardware interrupt handler;
Responsive to the reading of the semaphore reference, unblocking a task associated with the semaphore and executing context switching associated with the unblocked task.
2. A context switching method for real-time operating systems (RTOS), that execute on hardware with an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts, which never disables interrupts by handling semaphores released by hardware interrupt handlers in a low priority software interrupt, the method comprising:
Responsive to an interrupt occurring, releasing, by a hardware interrupt handler, a semaphore associated with the interrupt;
Accessing a shared bitmap variable comprising a plurality of bits in a memory, wherein one of the bits is associated with the semaphore;
Setting, by the hardware interrupt handler the bit associated with the semaphore, wherein the setting comprises:
Reading the shared bitmap variable from the memory,
Setting the bit associated with the semaphore in the shared bitmap variable,
Writing back the shared bitmap variable to the memory,
Responsive to the setting of the bit associated with the semaphore, activating a lower priority software interrupt handler;
Performing, by the low priority software interrupt handler a binary search on the shared bit map variable to discover which bit has been set;
Responsive to the discovering of the set bit, unblocking a task associated with the semaphore and executing context switching associated with the unblocked task.