IP Library › Granted Patent US 11,508,302
Granted Patent B2
US 11,508,302 · App. 17/519,592 · Granted Nov 22, 2022

Method for driving display panel and related driver circuit

Inventors: Chieh-Hsiang Chang (Miaoli County, TW); Wen-Pin Tsai (Hsinchu, TW)
Assignee: NOVATEK Microelectronics Corp.
G09G3/3233G09G2300/0842G09G2310/0248G09G2310/0297G09G2310/08G09G2320/0233G09G2330/021
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Quick Facts
Patent No.
US 11,508,302
App. No.
17/519,592
Granted
Nov 22, 2022
Kind
B2
Abstract

A method for a driver circuit configured to drive a display panel includes steps of: outputting a plurality of control signals according to a first control timing scheme to control a multiplexing circuit comprising a plurality of switches disposed in the display panel in a first operation mode; and outputting the plurality of control signals according to a second control timing scheme to control the multiplexing circuit in a second operation mode. Wherein, the first control timing scheme comprises a pre-charge period in which the plurality of switches of the multiplexing circuit are turned on, and the second control timing scheme comprises no pre-charge period.

Claims (52)

1. A method for a driver circuit, the driver circuit being configured to drive a display panel, the method comprising:

outputting a plurality of control signals according to a first control timing scheme to control a multiplexing circuit comprising a plurality of switches disposed in the display panel in a first operation mode; and

outputting the plurality of control signals according to a second control timing scheme to control the multiplexing circuit in a second operation mode;

wherein the first control timing scheme comprises a pre-charge period in which the plurality of switches of the multiplexing circuit are turned on, and the second control timing scheme comprises no pre-charge period.

2. The method of claim 1 , wherein the first control timing scheme and the second control timing scheme further comprise a data output period in which the driver circuit time-divisionally outputs a plurality of data voltages, and the pre-charge period is prior to the data output period in the first control timing scheme.

3. The method of claim 2 , wherein in the first control timing scheme, the pre-charge period and the data output period are within a horizontal line period.

4. The method of claim 1 , wherein the first operation mode is a normal display mode and power consumption of the driver circuit in the first operation mode is greater than power consumption of the driver circuit in the second operation mode.

5. The method of claim 1 , wherein a pre-charge voltage is applied to a plurality of data lines of the display panel in the pre-charge period.

6. The method of claim 5 , wherein the display panel is an organic light-emitting diode (organic-LED, OLED) panel having a plurality of pixels driven through P-type transistors, and the pre-charge voltage is lower than a plurality of data voltages output to the plurality of pixels in a data output period following the pre-charge period.

7. The method of claim 5 , wherein the display panel is an organic light-emitting diode (organic-LED, OLED) panel having a plurality of pixels driven through N-type transistors, and the pre-charge voltage is higher than a plurality of data voltages output to the plurality of pixels in a data output period following the pre-charge period.

8. The method of claim 1 , wherein the second operation mode is an always-on-display (AOD) mode and power consumption of the driver circuit in the second operation mode is less than power consumption of the driver circuit in the first operation mode.

9. The method of claim 1 , wherein in the pre-charge period, all of the switches of the multiplexing circuit are in an on-status simultaneously.

10. A method for a driver circuit, the driver circuit being configured to drive a display panel, the method comprising:

selectively configuring one of a first control timing scheme and a second control timing scheme to a first operation mode;

selectively configuring one of the first control timing scheme and the second control timing scheme to a second operation mode;

outputting a plurality of control signals according to a first selected control timing scheme to control a multiplexing circuit comprising a plurality of switches disposed in the display panel in the first operation mode; and

outputting the plurality of control signals according to a second selected control timing scheme to control the multiplexing circuit in the second operation mode;

wherein the first control timing scheme comprises a pre-charge period in which the plurality of switches of the multiplexing circuit are turned on, and the second control timing scheme comprises no pre-charge period.

11. The method of claim 10 , wherein the first control timing scheme and the second control timing scheme further comprise a data output period in which the driver circuit time-divisionally outputs a plurality of data voltages, and the pre-charge period is prior to the data output period in the first control timing scheme.

12. The method of claim 11 , wherein in the first control timing scheme, the pre-charge period and the data output period are within a horizontal line period.

13. The method of claim 10 , wherein the first operation mode is a normal display mode and the second operation mode is an always-on-display (AOD) mode.

14. The method of claim 10 , wherein the first operation mode is a normal display mode and power consumption of the driver circuit in the first operation mode is greater than power consumption of the driver circuit in the second operation mode.

15. The method of claim 10 , wherein a pre-charge voltage is applied to a plurality of data lines of the display panel in the pre-charge period.

16. The method of claim 15 , wherein the display panel is an organic light-emitting diode (organic-LED, OLED) panel having a plurality of pixels driven through P-type transistors, and the pre-charge voltage is lower than a plurality of data voltages output to the plurality of pixels in a data output period following the pre-charge period.

17. The method of claim 15 , wherein the display panel is an organic light-emitting diode (organic-LED, OLED) panel having a plurality of pixels driven through N-type transistors, and the pre-charge voltage is higher than a plurality of data voltages output to the plurality of pixels in a data output period following the pre-charge period.

18. The method of claim 10 , wherein in the pre-charge period, all of the switches of the multiplexing circuit are in an on-status simultaneously.

19. A driver circuit configured to drive a display panel, the driver circuit being configured to:

output a plurality of control signals according to a first control timing scheme to control a multiplexing circuit comprising a plurality of switches disposed in the display panel in a first operation mode; and

output the plurality of control signals according to a second control timing scheme to control the multiplexing circuit in a second operation mode;

wherein the first control timing scheme comprises a pre-charge period in which the plurality of switches of the multiplexing circuit are turned on, and the second control timing scheme comprises no pre-charge period.

20. The driver circuit of claim 19 , wherein the first control timing scheme and the second control timing scheme further comprise a data output period in which the driver circuit time-divisionally outputs a plurality of data voltages, and the pre-charge period is prior to the data output period in the first control timing scheme.

21. The driver circuit of claim 20 , wherein in the first control timing scheme, the pre-charge period and the data output period are within a horizontal line period.

22. The driver circuit of claim 19 , wherein the first operation mode is a normal display mode and power consumption of the driver circuit in the first operation mode is greater than power consumption of the driver circuit in the second operation mode.

23. The driver circuit of claim 19 , wherein a pre-charge voltage is applied to a plurality of data lines of the display panel in the pre-charge period.

24. The driver circuit of claim 23 , wherein the display panel is an organic light-emitting diode (organic-LED, OLED) panel having a plurality of pixels driven through P-type transistors, and the pre-charge voltage is lower than a plurality of data voltages output to the plurality of pixels in a data output period following the pre-charge period.

25. The driver circuit of claim 23 , wherein the display panel is an organic light-emitting diode (organic-LED, OLED) panel having a plurality of pixels driven through N-type transistors, and the pre-charge voltage is higher than a plurality of data voltages output to the plurality of pixels in a data output period following the pre-charge period.

26. The driver circuit of claim 19 , wherein the second operation mode is an always-on-display (AOD) mode and power consumption of the driver circuit in the second operation mode is less than power consumption of the driver circuit in the first operation mode.

27. The driver circuit of claim 19 , wherein in the pre-charge period, all of the switches of the multiplexing circuit are in an on-status simultaneously.

28. A driver circuit configured to drive a display panel, the driver circuit being configured to:

selectively configure one of a first control timing scheme and a second control timing scheme to a first operation mode;

selectively configure one of the first control timing scheme and the second control timing scheme to a second operation mode;

output a plurality of control signals according to a first selected control timing scheme to control a multiplexing circuit comprising a plurality of switches disposed in the display panel in the first operation mode; and

output the plurality of control signals according to a second selected control timing scheme to control the multiplexing circuit in the second operation mode;

wherein the first control timing scheme comprises a pre-charge period in which the plurality of switches of the multiplexing circuit are turned on, and the second control timing scheme comprises no pre-charge period.

29. The driver circuit of claim 28 , wherein the first control timing scheme and the second control timing scheme further comprise a data output period in which the driver circuit time-divisionally outputs a plurality of data voltages, and the pre-charge period is prior to the data output period in the first control timing scheme.

30. The driver circuit of claim 29 , wherein in the first control timing scheme, the pre-charge period and the data output period are within a horizontal line period.

31. The driver circuit of claim 28 , wherein the first operation mode is a normal display mode and the second operation mode is an always-on-display (AOD) mode.

32. The driver circuit of claim 28 , wherein the first operation mode is a normal display mode and power consumption of the driver circuit in the first operation mode is greater than power consumption of the driver circuit in the second operation mode.

33. The driver circuit of claim 28 , wherein a pre-charge voltage is applied to a plurality of data lines of the display panel in the pre-charge period.

34. The driver circuit of claim 33 , wherein the display panel is an organic light-emitting diode (organic-LED, OLED) panel having a plurality of pixels driven through P-type transistors, and the pre-charge voltage is lower than a plurality of data voltages output to the plurality of pixels in a data output period following the pre-charge period.

35. The driver circuit of claim 33 , wherein the display panel is an organic light-emitting diode (organic-LED, OLED) panel having a plurality of pixels driven through N-type transistors, and the pre-charge voltage is higher than a plurality of data voltages output to the plurality of pixels in a data output period following the pre-charge period.

36. The driver circuit of claim 28 , wherein in the pre-charge period, all of the switches of the multiplexing circuit are in an on-status simultaneously.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2021
From: CHANG, CHIEH-HSIANG; TSAI, WEN-PIN
To: NOVATEK MICROELECTRONICS CORP.
Reel/Frame 058026/0522 →
Continuity (2)
Provisional Application 63110380 · Nov 6, 2020
Related Publication 20220148505A1 · May 12, 2022