Semiconductor memory device capable of increasing flexibility of a column repair operation

1. A semiconductor memory device comprising:

a memory cell array including a plurality of memory blocks coupled to at least one word-line, wherein each of the plurality of memory blocks includes a plurality of dynamic memory cells;

at least one bit-line switch connected between a first half local input/output (I/O) line of a first memory block of the plurality of memory blocks and a second half local I/O line of the first memory block, wherein the first half local I/O line of the first memory block is connected to a first group of bit-lines of a plurality of bit-lines of the first memory block, and the second half local I/O line of the first memory block is connected to a second group of bit-lines of the plurality of bit-lines;

at least one block switch connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block among the plurality of memory blocks, wherein the first memory block and the second memory block are adjacent to each other; and

a column decoder including a repair circuit, wherein the repair circuit is configured to control a connection between the first half local I/O line of the first memory block and the second half local I/O line of the first memory block by applying a first switching control signal to the at least one bit-line switch, and is configured to control a connection between the second half local I/O line of the first memory block and the first half local I/O line of the second memory block by applying a second switching control signal to the at least one block switch,

wherein

the first group of bit-lines includes at least a first spare bit-line coupled to first spare cells among the plurality of dynamic memory cells,

the second group of bit-lines includes at least a second spare bit-line coupled to second spare cells among the plurality of dynamic memory cells,

the first group of bit-lines are connected to the first half local I/O line of the first memory block through first bit-line sense amplifiers,

the second group of bit-lines are connected to the second half local I/O line of the first memory block through second bit-line sense amplifiers, and

the first bit-line sense amplifiers are connected between the first group of bit-lines and the first half local I/O line, and the second bit-line sense amplifiers are connected between the second group of bit-lines and the second half local I/O line.

2. The semiconductor memory device of claim 1 , further comprising a local sense amplifier circuit corresponding to the first memory block,

wherein the local sense amplifier circuit is connected to the first half local I/O line of the first memory block and the second half local I/O line of the first memory block through the at least one bit-line switch, and

wherein the local sense amplifier circuit is connected to a global I/O line.

3. The semiconductor memory device of claim 1 , wherein the repair circuit is configured to connect the second half local I/O line of the first memory block and the first half local I/O line of the second memory block by applying the second switching control signal to the at least one block switch.

4. The semiconductor memory device of claim 3 , wherein if the second half local I/O line of the first memory block and the first half local I/O line of the second memory block are connected to each other, at least one spare bit-line of the second memory block is connected to a local sense amplifier circuit corresponding to the first memory block.

5. The semiconductor memory device of claim 1 , wherein the at least one bit-line switch includes:

a first bit-line switch connected between the first half local I/O line of the first memory block and a first node; and

a second bit-line switch connected between the first node and the second half local I/O line of the first memory block.

6. The semiconductor memory device of claim 5 , wherein the repair circuit is configured to apply the first switching control signal to the first bit-line switch and is configured to apply an inverted version of the first switching control signal to the second bit-line switch.

7. A semiconductor memory device comprising:

a memory cell array including a plurality of memory blocks coupled to at least one word-line, wherein each of the plurality of memory blocks includes a plurality of dynamic memory cells;

at least one bit-line switch coupled between a first half local input/output (I/O) line of a first memory block of the plurality of memory blocks and a second half local I/O line of the first memory block, wherein the first half local I/O line of the first memory block is connected to a first group of bit-lines of a plurality of bit-lines of the first memory block, and the second half local I/O line of the first memory block is connected to a second group of bit-lines of the plurality of bit-lines;

at least one block switch connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block among the plurality of memory blocks, wherein the first memory block and the second memory block are adjacent to each other; and

a column decoder configured to repair a first bit-line of the first memory block with at least one spare bit-line of the first memory block or with a spare bit-line of a memory block adjacent to the first memory block by controlling the at least one bit-line switch and the at least one block switch,

wherein

the first bit-line is coupled to a defective cell of the plurality of dynamic memory cells,

the first group of bit-lines includes at least a first spare bit-line coupled to first spare cells among the plurality of dynamic memory cells,

the second group of bit-lines includes at least a second spare bit-line coupled to second spare cells among the plurality of dynamic memory cells, and

if a second bit-line and a third bit-line are connected to defective cells, the column decoder is configured to:

repair the first bit-line with the first spare bit-line of the first memory block;

repair the second-bit-line with the second spare bit-line of the first memory block; and

repair the third bit-line with a first spare bit-line of the second memory block which is adjacent to the first memory block in a direction of the second half local I/O line of the first memory block.

8. The semiconductor memory device of claim 7 , wherein the column decoder includes a repair circuit, and

wherein the repair circuit is configured to control a connection between the first half local I/O line of the first memory block and the second half local I/O line of the first memory block by applying a first switching control signal to the at least one bit-line switch and is configured to control a connection between the second half local I/O line of the first memory block and the first half local I/O line of the second memory block by applying a second switching control signal to the at least one block switch.

9. The semiconductor memory device of claim 7 , wherein the column decoder is configured to repair the first bit-line of the first memory block with the first spare bit-line of the first memory block.

10. The semiconductor memory device of claim 7 , wherein the column decoder is configured to repair the first bit-line of the first memory block with a second spare bit-line of a third memory block which is adjacent to the first memory block in a direction of the first half local I/O line of the first memory block.

11. The semiconductor memory device of claim 7 , wherein the column decoder is configured to repair the first bit-line of the first memory block with a second spare bit-line of the second memory block which is adjacent to the first memory block in a direction of the second half local I/O line of the first memory block.

12. The semiconductor memory device of claim 7 , wherein the column decoder is configured to repair the first bit-line of the first memory block with a second spare bit-line of a third memory block which is adjacent to the second memory block in a direction of the second half local I/O line of the first memory block, and

wherein the second memory block is adjacent to the first memory block in a direction of the second half local I/O line of the first memory block.

13. The semiconductor memory device of claim 7 , wherein if four or more bit-lines of the first memory block are connected to defective cells, the column decoder is configured to repair the four or more bit-lines with spare bit-lines of the first memory block, the second memory block, a third memory block, and a fourth memory block,

wherein the second memory block is adjacent to the first memory block in a direction of the second half local I/O line of the first memory block,

wherein the third memory block is adjacent to the first memory block in a direction of the first half local I/O line of the first memory block, and

wherein the fourth memory block is adjacent to the third memory block in a direction of the first half local I/O line of the first memory block.

14. A semiconductor memory device comprising:

a memory cell array including a plurality of memory blocks coupled to at least one word-line, wherein each of the plurality of memory blocks includes a plurality of dynamic memory cells;

at least one bit-line switch coupled between a first half local input/output (I/O) line of a first memory block of the plurality of memory blocks and a second half local I/O line of the first memory block, wherein the first half local I/O line of the first memory block is connected to a first group of bit-lines of a plurality of bit-lines of the first memory block, and the second half local I/O line of the first memory block is connected to a second group of bit-lines of the plurality of bit-lines;

at least one block switch connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block among the plurality of memory blocks, wherein the first memory block and the second memory block are adjacent to each other; and

a column decoder configured to repair a first bit-line of the first memory block with at least one spare bit-line of the first memory block or with a spare bit-line of a memory block adjacent to the first memory block by controlling the at least one bit-line switch and the at least one block switch,

wherein

the first bit-line is coupled to a defective cell of the plurality of dynamic memory cells,

the first group of bit-lines includes at least a first spare bit-line coupled to first spare cells among the plurality of dynamic memory cells,

the second group of bit-lines includes at least a second spare bit-line coupled to second spare cells among the plurality of dynamic memory cells, and

if the first bit-line of the first memory block, a second bit-line of the first memory block, a first bit-line of the second memory block, and a second bit-line of the second memory block are connected to defective cells, the column decoder is configured to:

repair the first bit-line of the first memory block with the first spare bit-line of the first memory block;

repair the second bit-line of the first memory block with the second spare bit-line of the first memory block;

repair the first bit-line of the second memory block with a first spare bit-line of the second memory block; and

repair the second bit-line of the second memory block with a second spare bit-line of the second memory block.