Grid structure to reduce domain size in ferroelectric memory device

1. An integrated chip, comprising:

a pair of source/drain regions disposed in a substrate;

a gate dielectric layer disposed over the substrate and laterally between the pair of source/drain regions; and

a ferroelectric structure overlying the gate dielectric layer, wherein the ferroelectric structure comprises a ferroelectric layer and a grid structure, wherein the ferroelectric layer comprises a plurality of segments laterally offset from one another, wherein the grid structure laterally encloses each segment of the ferroelectric layer, wherein the ferroelectric layer comprises a first dielectric material and the grid structure comprises a second dielectric material different than the first dielectric material.

2. The integrated chip according to claim 1 , further comprising:

a first conductive structure disposed between the ferroelectric structure and the gate dielectric layer;

a second conductive structure overlying the ferroelectric structure; and

a gate electrode disposed between the first conductive structure and the gate dielectric layer.

3. The integrated chip according to claim 2 , wherein the grid structure and the segments of the ferroelectric layer continuously extend from a top surface of the first conductive structure to a bottom surface of the second conductive structure.

4. The integrated chip according to claim 1 , wherein the grid structure continuously laterally wraps around an outer perimeter of the ferroelectric layer.

5. The integrated chip according to claim 1 , wherein a maximum width of the ferroelectric layer is less than a maximum width of the grid structure.

6. The integrated chip according to claim 1 , wherein the grid structure directly contacts the gate dielectric layer.

7. The integrated chip according to claim 1 , further comprising:

a gate electrode overlying the ferroelectric structure, wherein the grid structure directly contacts the gate electrode.

8. The integrated chip according to claim 1 , wherein the second dielectric material is a non-ferroelectric material.

9. An integrated chip, comprising:

a semiconductor device disposed on a substrate;

a first inter-level dielectric (ILD) structure overlying the semiconductor device and the substrate; and

a polarization switching structure overlying the first ILD structure and electrically coupled to the semiconductor device, wherein the polarization switching structure comprises a ferroelectric structure disposed between a first conductive structure and a second conductive structure, wherein the ferroelectric structure comprises a ferroelectric layer and a grid structure, wherein the grid structure laterally encloses an outer perimeter of the ferroelectric layer, wherein the ferroelectric layer comprises a first material and the grid structure comprises a second material different than the first material, wherein the grid structure comprises a plurality of sidewalls defining a plurality of openings, wherein the ferroelectric layer fills the plurality of openings.

10. The integrated chip of claim 9 , wherein the grid structure comprises a plurality of elongated grid segments extending laterally in a first direction and a plurality of short grid segments extending laterally in a second direction that is substantially orthogonal to the first direction, wherein the short grid segments continuously extend between adjacent pairs of the elongated grid segments.

11. The integrated chip of claim 10 , wherein the ferroelectric layer continuously laterally extends between pairs of the elongated grid segments.

12. The integrated chip of claim 10 , wherein the ferroelectric layer comprises a plurality of pillar structures, wherein the pillar structures are alternatingly spaced between the short grid segments.

13. The integrated chip of claim 12 , wherein a width of the pillar structures is greater than a width of the short grid segments.

14. The integrated chip of claim 10 , wherein a width of the elongated grid segments is greater than a width of the ferroelectric layer.

15. The integrated chip of claim 9 , wherein the first material is hafnium oxide and the second material is silicon dioxide, tetra-ethyl-ortho-silicate (TEOS), silicon oxynitride, silicon oxycarbide, or silicon nitride.

16. An integrated chip, comprising:

a semiconductor device disposed on a substrate;

a dielectric structure overlying the semiconductor device and the substrate; and

a polarization switching structure overlying the dielectric structure and electrically coupled to the semiconductor device, wherein the polarization switching structure comprises a ferroelectric structure disposed between a first conductive structure and a second conductive structure, wherein the ferroelectric structure comprises a ferroelectric layer and a dielectric grid structure, wherein the dielectric grid structure laterally encloses an outer perimeter of the ferroelectric layer, wherein the dielectric grid structure comprises a plurality of elongated grid segments extending laterally in a first direction and a plurality of short grid segments extending laterally in a second direction that is substantially orthogonal to the first direction, wherein the short grid segments continuously extend between adjacent pairs of the elongated grid segments.

17. The integrated chip of claim 16 , wherein the ferroelectric layer comprises a plurality of pillar structures alternatingly spaced between the short grid segments, wherein a width of a first elongated grid segment in the plurality of elongated grid segments is greater than a width of a first pillar structure in the plurality of pillar structures.

18. The integrated chip of claim 17 , wherein a length of the first elongated grid segment is less than a length of the first pillar structure.

19. The integrated chip of claim 16 , wherein a height of the ferroelectric layer is equal to a height of the dielectric grid structure.

20. The integrated chip of claim 16 , wherein the dielectric grid structure comprises a single continuous material different from that of the ferroelectric layer.