Single photon avalanche diode device
The present invention provides a single photon avalanche diode device. The device has a logic substrate comprising an upper surface. The device has a sensor substrate bonded to an upper surface of the logic substrate. In an example, the sensor substrate comprises a plurality of pixel elements spatially disposed to form an array structure. In an example, each of the pixel elements has a passivation material, an epitaxially grown silicon material, an implanted p-type material configured in a first portion of the epitaxially grown material, an implanted n-type material configured in a second portion of the epitaxially grown material, and a junction region configured from the implanted p-type material and the implanted n-type material.
1. A single photon avalanche diode device comprising:
a logic substrate comprising an upper surface;
a sensor substrate bonded to the upper surface of the logic substrate, the sensor substrate comprising a plurality of pixel elements spatially disposed to form an array structure, each of the pixel elements comprising:
a passivation material comprising an opening;
an epitaxially grown p-type silicon material;
an implanted p-type material configured in a first portion of the epitaxially grown material; and
an implanted n-type material configured in a second portion of the epitaxially grown material;
a junction region configured from the implanted p-type material and the implanted n-type material; and
a deep trench region bordering the pixel element, the trench region comprising a fill material, a surrounding charge material, and a surrounding insulating material;
a first contact region on a first side of the sensor substrate coupled to the implanted p-type material, the first contact region being at least partially exposed through the opening;
a second contact region on a second side of the sensor substrate coupled to the implanted n-type material and the logic substrate; and
whereupon the charge material is configured with a negative charge to cause a plurality of holes within a vicinity of the surrounding charge material.
2. The device of claim 1 wherein each of the pixel elements comprises an anti-reflective material overlying the passivation material.
3. The device of claim 1 wherein each of the pixel elements having a size ranging from 1 micron to about 100 microns.
4. The device of claim 1 wherein the passivation material comprises an oxide material, a high-K dielectric material, a nitride material, or a polyimide material.
5. The device of claim 1 wherein the implanted p-type material comprises a boron material having a concentration density of 1E15 atoms/cm3 to 1E18 atoms/cm3.
6. The device of claim 1 wherein the implanted n-type material comprises a phosphorous entity or an arsenic entity having a concentration density of 1E17 atoms/cm3 to 1E19 atoms/cm3.
7. The device of claim 1 wherein the array structure is N by M, where N is 1 and greater and M is 1 and greater.
8. The device of claim 1 wherein the fill material comprises a metal material, a semiconductor material, or an insulating material.
9. The device of claim 1 wherein the implanted p-type material and the implanted n-type material are configured within a vicinity of the logic substrate of the pixel element.
10. The device of claim 1 wherein the logic substrate comprises a plurality of CMOS cells.
11. The device of claim 1 wherein each of the pixel elements comprises a plurality of nano-structures configured overlying the aperture region to facilitate trapping of a photon coming in contact with the nano-structure, the nano-structure being configured from a silicon material.
12. The device of claim 1 wherein each of the pixel elements comprises a plurality of nano-structures configured within a vicinity of an interface to the upper surface to facilitate trapping of a photon coming in contact with the nano-structure.
13. The device of claim 1 wherein each of the pixel elements comprises a reflective material configured on an opposite side of the aperture region to facilitate reflecting a photon from a underlying region to the junction region.
14. A single photon avalanche diode device comprising:
a logic substrate comprising an upper surface;
a sensor substrate comprising a back side and a front side, the front side being bonded to the upper surface of the logic substrate, the sensor substrate comprising a plurality of pixel elements spatially disposed to form an array structure, each of the pixel elements comprising:
a passivation layer overlaying the back side and comprising an opening;
an epitaxially grown p-type silicon material;
an implanted n-type material configured in a first portion of the epitaxially grown material;
an implanted p-type material overlying the n-type material and configured in a second portion of the epitaxially grown material;
a junction region configured from the implanted p-type material and the implanted n-type material; and
a deep trench region bordering the pixel element, the trench region comprising a trench opening, a surrounding insulating material, a surrounding charge material, and a fill material; and
a first contact region on the back side of the sensor substrate coupled to the implanted n-type material through the opening, the first contact region being at least partially exposed and positioned outside the epitaxially grown p-type silicon material; and
a second contact region on a front side of the sensor substrate coupled to the implanted p-type material; and
whereupon the charge material is configured with a negative fixed charge to cause a plurality of holes within a vicinity of the surrounding charge material.
15. The device of claim 14 wherein each of the pixel elements comprises an anti-reflective material overlying the passivation material.
16. The device of claim 14 wherein each of the pixel elements having a size ranging from 1 micron to about 100 microns.
17. The device of claim 14 wherein the passivation material comprises an oxide material, a high-K dielectric material, a nitride material, or a polyimide material.
18. The device of claim 14 wherein the implanted p-type material comprises a boron material having a concentration density of 1E15 atoms/cm3 to 1E18 atoms/cm3.
19. The device of claim 14 wherein the implanted n-type material comprises a phosphorous entity or an arsenic entity having a concentration density of 1E17 atoms/cm3 to 1E19 atoms/cm3.
20. The device of claim 14 wherein the array structure is N by M, where N is 1 and greater and M is 1 and greater.
21. The device of claim 14 wherein the fill material comprises a metal material, a semiconductor material, or an insulating material.
22. The device of claim 14 wherein the implanted p-type material and the implanted n-type material are configured within a vicinity of an aperture region of the pixel element.
23. The device of claim 14 wherein the sensor substrate comprises a plurality of CMOS cells.
24. The device of claim 14 wherein each of the pixel elements comprises a plurality of nano-structures configured overlying the aperture region to facilitate trapping of a photon coming in contact with the nano-structure, the nano-structure being configured from a silicon material.
25. The device of claim 14 wherein each of the pixel elements comprises a plurality of nano-structures configured within a vicinity of an interface to the upper surface to facilitate trapping of a photon coming in contact with the nano-structure.
26. The device of claim 14 wherein each of the pixel elements comprises a reflective material configured on an opposite side of the aperture region to facilitate reflecting a photon from a backside region to the junction region.