Sigma-delta analogue to digital converter
A sigma-delta ADC comprising: a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal; a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal; an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal. The sigma-delta ADC also includes a feedback-current-block, which comprises: a first-feedback-transistor having a conduction channel; a second-feedback-transistor having a conduction channel; a first-feedback-switch; a second-feedback-switch; a first-feedback-current-source; and a second-feedback-current-source.
1. A sigma-delta ADC comprising:
a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal;
a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal;
an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal;
a first-amplifier-stage comprising:
a first-amplifier-first-input-terminal;
a first-amplifier-second-input-terminal;
a first-amplifier-first-output-terminal;
a first-amplifier-second-output-terminal;
a first-input-resistor connected in series between the first-input-terminal and the first-amplifier-first-input-terminal;
a second-input-resistor connected in series between the second-input-terminal and the first-amplifier-second-input-terminal;
a first-amplifier-first-transistor comprising:
a control-terminal, that is connected to the first-amplifier-first-input-terminal and is configured to receive a high-voltage first-amplifier-first-input-signal;
a first-conduction-channel-terminal, that is configured to be connected to a high-voltage supply;
a second-conduction-channel-terminal, that is configured to provide a low-voltage signal for setting the voltage at the first-amplifier-first-output-terminal;
a first-amplifier-second-transistor comprising:
a control-terminal, that is connected to the first-amplifier-second-input-terminal and is configured to receive a high-voltage first-amplifier-second-input-signal;
a first-conduction-channel-terminal, that is configured to be connected to a high-voltage supply;
a second-conduction-channel-terminal, that is configured to provide a low-voltage signal for setting the voltage at the first-amplifier-second-output-terminal; and
a first-integration-capacitor connected between the first-amplifier-first-output-terminal and the first-amplifier-first-input-terminal;
a second-integration-capacitor connected between the first-amplifier-second-output-terminal and the first-amplifier-second-input-terminal;
a threshold-block that is configured to:
receive signals from the first-amplifier-first-output-terminal and the first-amplifier-second-output-terminal; and
provide the output-digital-signal to the output-terminal; and
a feedback-current-block, which comprises:
a first-feedback-transistor having a conduction channel;
a second-feedback-transistor having a conduction channel;
a first-feedback-switch;
a second-feedback-switch;
a first-feedback-current-source; and
a second-feedback-current-source;
wherein:
each of the following components is connected in series between the first-amplifier-first-input-terminal and a reference-terminal: the conduction channel of the first-feedback-transistor; the first-feedback-switch; and the first-feedback-current-source; and
each of the following components is connected in series between the first-amplifier-second-input-terminal and the reference-terminal: the conduction channel of the second-feedback-transistor; the second-feedback-switch; and the second-feedback-current-source.
2. The sigma-delta ADC of claim 1 , wherein a high voltage is a voltage that is greater than or equal to 10V, 40V, 80V or 120V.
3. The sigma-delta ADC of claim 1 , wherein a low voltage is a voltage that is less than or equal to 5V, 3V, 1.8V or 1V.
4. The sigma-delta ADC of claim 1 , wherein:
the first-feedback-transistor comprises a high voltage device; and
the first-feedback-current-source comprises a low voltage device.
5. The sigma-delta ADC of claim 4 , wherein:
the low voltage device is one that is suitable for handling a low voltage signal, and a low voltage is a voltage that is less than or equal to 5V, 3V, 1.8V or 1V; and
the high voltage device is one that is capable of handling a high voltage signal, and a high voltage is a voltage that is greater than or equal to 10V, 40V, 80V or 120V.
6. The sigma-delta ADC of claim 1 , wherein:
the second-feedback-transistor comprises a high voltage device; and
the second-feedback-current-source comprises a low voltage device.
7. The sigma-delta ADC of claim 1 , wherein:
the first-amplifier-first-transistor comprises a first-amplifier-first-cascode; and
the first-amplifier-second-transistor comprises a first-amplifier-second-cascode.
8. The sigma-delta ADC of claim 7 , wherein:
the low voltage device is one that is suitable for handling a low voltage signal, and a low voltage is a voltage that is less than or equal to 5V, 3V, 1.8V or 1V; and
the high voltage device is one that is capable of handling a high voltage signal, and a high voltage is a voltage that is greater than or equal to 10V, 40V, 80V or 120V.
9. The sigma-delta ADC of claim 1 , wherein:
the first-amplifier-first-cascode comprises a high voltage device and a low voltage device; and
the first-amplifier-second-cascode comprises a high voltage device and a low voltage device.
10. The sigma-delta ADC of claim 1 , wherein the first-amplifier-first-transistor and the first-amplifier-second-transistor are provided as a differential pair.
11. The sigma-delta ADC of claim 1 , wherein:
the first-amplifier-first-transistor comprises a pmos FET; and
the first-amplifier-second-transistor comprises a pmos FET.
12. The sigma-delta ADC of claim 11 , wherein:
the low voltage device is one that is suitable for handling a low voltage signal; and
the high voltage device is one that is capable of handling a high voltage signal.
13. The sigma-delta ADC of claim 1 , wherein:
the first-feedback-transistor comprises a nmos FET; and
the second-feedback-transistor comprises a nmos FET.
14. The sigma-delta ADC of claim 13 , wherein a high voltage is a voltage that is greater than or equal to 10V, 40V, 80V or 120V.
15. The sigma-delta ADC of claim 13 , wherein a low voltage is a voltage that is less than or equal to 5V, 3V, 1.8V or 1V.
16. The sigma-delta ADC of claim 1 , wherein:
the first-feedback-switch and the first-feedback-current-source are both connected in series between: (i) a first terminal of the conduction channel of the first-feedback-transistor; and (ii) the reference-terminal;
a second terminal of the conduction channel of the first-feedback-transistor is connected to the first-amplifier-first-input-terminal;
the second-feedback-switch and the second-feedback-current-source are both connected in series between: (i) a first terminal of the conduction channel of the second-feedback-transistor; and (ii) the reference-terminal; and
a second terminal of the conduction channel of the second-feedback-transistor is connected to the first-amplifier-second-input-terminal.
17. The sigma-delta ADC of claim 1 , wherein the sigma-delta ADC is a continuous-time ADC.
18. The sigma-delta ADC of claim 1 , further comprising one or more further amplifier-stages provided in series with the first-amplifier-stage between (i) the first-input-terminal and the second-input-terminal, and (ii) the threshold-block.
19. A battery management system for a vehicle, wherein the battery management system comprises a sigma-delta ADC, wherein the sigma-delta ADC comprises;
a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal;
a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal;
an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal;
a first-amplifier-stage comprising:
a first-amplifier-first-input-terminal;
a first-amplifier-second-input-terminal;
a first-amplifier-first-output-terminal;
a first-amplifier-second-output-terminal;
a first-input-resistor connected in series between the first-input-terminal and the first-amplifier-first-input-terminal;
a second-input-resistor connected in series between the second-input-terminal and the first-amplifier-second-input-terminal;
a first-amplifier-first-transistor comprising:
a control-terminal, that is connected to the first-amplifier-first-input-terminal and is configured to receive a high-voltage first-amplifier-first-input-signal;
a first-conduction-channel-terminal, that is configured to be connected to a high-voltage supply;
a second-conduction-channel-terminal, that is configured to provide a low-voltage signal for setting the voltage at the first-amplifier-first-output-terminal;
a first-amplifier-second-transistor comprising:
a control-terminal, that is connected to the first-amplifier-second-input-terminal and is configured to receive a high-voltage first-amplifier-second-input-signal;
a first-conduction-channel-terminal, that is configured to be connected to a high-voltage supply;
a second-conduction-channel-terminal, that is configured to provide a low-voltage signal for setting the voltage at the first-amplifier-second-output-terminal; and
a first-integration-capacitor connected between the first-amplifier-first-output-terminal and the first-amplifier-first-input-terminal;
a second-integration-capacitor connected between the first-amplifier-second-output-terminal and the first-amplifier-second-input-terminal;
a threshold-block that is configured to:
receive signals from the first-amplifier-first-output-terminal and the first-amplifier-second-output-terminal; and
provide the output-digital-signal to the output-terminal; and
a feedback-current-block, which comprises:
a first-feedback-transistor having a conduction channel;
a second-feedback-transistor having a conduction channel;
a first-feedback-switch;
a second-feedback-switch;
a first-feedback-current-source; and
a second-feedback-current-source;
wherein:
each of the following components is connected in series between the first-amplifier-first-input-terminal and a reference-terminal: the conduction channel of the first-feedback-transistor; the first-feedback-switch; and the first-feedback-current-source; and
each of the following components is connected in series between the first-amplifier-second-input-terminal and the reference-terminal: the conduction channel of the second-feedback-transistor; the second-feedback-switch; and the second-feedback-current-source.
20. A vehicle comprising a battery management system, wherein the battery management system comprises a sigma-delta ADC, wherein the sigma-delta ADC comprises:
a first-input-terminal configured to receive a first-high-voltage-analogue-input-signal;
a second-input-terminal configured to receive a second-high-voltage-analogue-input-signal;
an output-terminal configured to provide an output-digital-signal, wherein the output-digital-signal is representative of the difference between the first-high-voltage-analogue-input-signal and the second-high-voltage-analogue-input-signal;
a first-amplifier-stage comprising:
a first-amplifier-first-input-terminal;
a first-amplifier-second-input-terminal;
a first-amplifier-first-output-terminal;
a first-amplifier-second-output-terminal;
a first-input-resistor connected in series between the first-input-terminal and the first-amplifier-first-input-terminal;
a second-input-resistor connected in series between the second-input-terminal and the first-amplifier-second-input-terminal;
a first-amplifier-first-transistor comprising:
a control-terminal, that is connected to the first-amplifier-first-input-terminal and is configured to receive a high-voltage first-amplifier-first-input-signal;
a first-conduction-channel-terminal, that is configured to be connected to a high-voltage supply;
a second-conduction-channel-terminal, that is configured to provide a low-voltage signal for setting the voltage at the first-amplifier-first-output-terminal;
a first-amplifier-second-transistor comprising:
a control-terminal, that is connected to the first-amplifier-second-input-terminal and is configured to receive a high-voltage first-amplifier-second-input-signal;
a first-conduction-channel-terminal, that is configured to be connected to a high-voltage supply;
a second-conduction-channel-terminal, that is configured to provide a low-voltage signal for setting the voltage at the first-amplifier-second-output-terminal; and
a first-integration-capacitor connected between the first-amplifier-first-output-terminal and the first-amplifier-first-input-terminal;
a second-integration-capacitor connected between the first-amplifier-second-output-terminal and the first-amplifier-second-input-terminal;
a threshold-block that is configured to:
receive signals from the first-amplifier-first-output-terminal and the first-amplifier-second-output-terminal; and
provide the output-digital-signal to the output-terminal; and
a feedback-current-block, which comprises:
a first-feedback-transistor having a conduction channel;
a second-feedback-transistor having a conduction channel;
a first-feedback-switch;
a second-feedback-switch;
a first-feedback-current-source; and
a second-feedback-current-source;
wherein:
each of the following components is connected in series between the first-amplifier-first-input-terminal and a reference-terminal: the conduction channel of the first-feedback-transistor; the first-feedback-switch; and the first-feedback-current-source; and
each of the following components is connected in series between the first-amplifier-second-input-terminal and the reference-terminal: the conduction channel of the second-feedback-transistor; the second-feedback-switch; and the second-feedback-current-source.