Semiconductor device, and electronic device
View Patent ↗A semiconductor device and electronic device with reduced power consumption are provided. The semiconductor device includes an encoder, a decoder, and a source driver circuit. An output terminal of the encoder is electrically connected to an input terminal of the source driver circuit, and an output terminal of the source driver circuit is electrically connected to an input terminal of the decoder. The encoder converts input image data into feature-extracted image data, and the decoder restores the feature-extracted image data to the original image data. In addition, provision of a circuit that performs convolution processing using a weight filter for the encoder enables calculation using a convolutional neural network.
1. A semiconductor device comprising:
an encoder;
a decoder; and
a source driver circuit,
wherein an output terminal of the encoder is electrically connected to an input terminal of the source driver circuit,
wherein an output terminal of the source driver circuit is electrically connected to an input terminal of the decoder,
wherein the encoder is configured to convert first image data into feature-extracted second image data when a first analog signal corresponding to the first image data is input to the encoder,
wherein the encoder is configured to output the second image data as a second analog signal from the output terminal of the encoder,
wherein the decoder is configured to restore the second image data into the first image data when the second analog signal is input to the input terminal of the decoder,
wherein the decoder is configured to output the restored first image data as a third analog signal from an output terminal of the decoder,
wherein the encoder comprises a neural network configured to perform convolution processing using a weight filter,
wherein the encoder comprises a memory cell array and a shift register,
wherein the memory cell array is configured to store a filter value of the weight filter,
wherein the shift register is configured to sequentially output the first image data for every pixel region to the memory cell array,
wherein the convolution processing comprises product-sum operation using the first image data and the filter value,
wherein the first image data comprises n rows and m columns of pixel data,
wherein the pixel region comprises t rows and s columns,
wherein the shift register comprises t×m stages of retention circuits,
wherein the shift register is configured to output t×s of the pixel data from the first image data to the memory cell array at a time,
wherein n and m are each an integer greater than or equal to 1, and
wherein t is an integer greater than or equal to 1 and less than or equal to n, and s is an integer greater than or equal to 1 and less than or equal to m.
2. The semiconductor device according to claim 1 ,
wherein the memory cell array comprises a first transistor, and
wherein the first transistor comprises a metal oxide in a channel formation region.
3. The semiconductor device according to claim 1 ,
further comprising an autoencoder,
wherein the encoder and the decoder are comprised in the autoencoder.
4. The semiconductor device according to claim 1 ,
further comprising an analog buffer circuit,
wherein an input terminal of the analog buffer circuit is electrically connected to the output terminal of the decoder.
5. The semiconductor device according to claim 1 ,
wherein the source driver circuit comprises a latch circuit, and
wherein the latch circuit is configured to store the second image data output from the encoder, and
wherein the latch circuit is configured to output the second image data to the decoder.
6. The semiconductor device according to claim 5 ,
wherein the latch circuit comprises a second transistor, and
wherein the second transistor comprises a metal oxide in a channel formation region.