Method, product, and system for integrating a hardware accelerator with an extensible processor
An approach includes the use of a description of instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions. In some embodiments, the instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions are described using a single language. These descriptions are then compiled into other languages for use in tool chains for generating simulators (a hardware and instruction set simulator and a hardware accelerator simulator). In some embodiments, the approach illustrated herein can be combined with state machine functionality to manage the execution of instructions that require multiple states. In some embodiments, the approach illustrated herein can be combined with an external register file for transferring information between a processor and a hardware accelerator.
1. A method, comprising:
receiving a description of a processor extension in a first high-level language and a description of a hardware accelerator in the same first high-level language;
receiving an application program comprising instructions in a second high-level language; and
implementing a compilation process to generate a verification test bench using the description of the processor extension in the same first high-level language, the description of the hardware accelerator in the same first high-level language, and the application program.
2. The method of claim 1 , wherein implementing the compilation process comprises generation of machine code from the application program, and a simulator dynamic link library, a hardware representation, an electronic design automation script, and the verification test bench.
3. The method of claim 1 , wherein implementing the compilation process comprises generating source code for a cross-compiler and an instruction set architecture dynamic link library.
4. The method of claim 3 , wherein the instruction set architecture dynamic link library and the instructions of the application program are translated into machine code with the cross-compiler.
5. The method of claim 1 , wherein implementing the compilation process comprises generating cycle-accurate simulator source code.
6. The method of claim 5 , wherein the cycle-accurate simulator source code is compiled to generate a simulator dynamic link library, and the simulator dynamic link library is used to simulate operation of the hardware accelerator and an instruction set for the hardware accelerator.
7. The method of claim 1 , further comprising implementing a verification phase, wherein the verification phase comprises:
identifying machine code, a simulator dynamic link library, a representation of the hardware accelerator, an electronic design automation script, and the verification test bench; and
executing a simulation process using the machine code, the simulator dynamic link library, the representation of the hardware accelerator, and the electronic design automation script, at the verification test bench.
8. The method of claim 1 , wherein implementing the compilation process to generate the verification test bench supports generating a hardware accelerator representation that includes one or more state machines for executing multi-cycle instructions without control of each sub-step by an extensible processor.
9. The method of claim 1 , wherein one or more multi-cycle instructions are associated with respective cycle latencies, and wherein a cross-compiler supports scheduling of operations at an extensible processor while at least one of the one or more multi-cycle instructions are to be executed at the hardware accelerator.
10. A non-transitory computer readable medium, having stored thereon a set of instructions, which when executed by a processor cause a set of acts, the set of acts comprising:
identifying a description of a processor extension in a first high-level language and a description of a hardware accelerator in the same first high-level language;
identifying an application program comprising instructions in a second high-level language; and
executing a compilation process to generate a verification test bench using the description of the processor extension in the same first high-level language, the description of the hardware accelerator in the same first high-level language, and the application program.
11. The computer readable medium of claim 10 , wherein implementing the compilation process comprises generation of machine code from the application program, and a simulator dynamic link library, a hardware representation, an electronic design automation script, and the verification test bench.
12. The computer readable medium of claim 10 , wherein implementing the compilation process comprises generating source code for a cross-compiler and an instruction set architecture dynamic link library.
13. The computer readable medium of claim 12 , wherein the instruction set architecture dynamic link library and the instructions of the application program are translated into machine code with the cross-compiler.
14. The computer readable medium of claim 10 , wherein implementing the compilation process comprises generating cycle-accurate simulator source code.
15. The computer readable medium of claim 14 , wherein the cycle-accurate simulator source code is compiled to generate a simulator dynamic link library, and the simulator dynamic link library is used to simulate operation of the hardware accelerator and an instruction set for the hardware accelerator.
16. The computer readable medium of claim 10 , wherein the set of acts further comprise implementing a verification phase, wherein the verification phase comprises:
identifying machine code, a simulator dynamic link library, a representation of the hardware accelerator, an electronic design automation script, and the verification test bench; and
executing a simulation process using the machine code, the simulator dynamic link library, the representation of the hardware accelerator, and the electronic design automation script, at the verification test bench.
17. The computer readable medium of claim 10 , wherein executing the compilation process to generate the verification test bench supports generating a hardware accelerator representation that includes one or more state machines for executing multi-cycle instructions without control of each sub-step by an extensible processor.
18. The computer readable medium of claim 10 , wherein one or more multi-cycle instructions are associated with respective cycle latencies, and wherein a cross-compiler supports scheduling of operations at an extensible processor while at least one of the one or more multi-cycle instructions are to be executed at the hardware accelerator.
19. A computing system comprising:
a memory for storing a set of instructions;
a processor for executing the set of instructions to provide an electronic design system, the electronic design system executing the set of instructions to cause a set of acts, the set of acts comprising:
retrieving a description of a processor extension in a first high-level language and a description of a hardware accelerator in the same first high-level language;
retrieving an application program comprising instructions in a second high-level language; and
generating a verification test bench by implementing a compilation process using the description of the processor extension in the same first high-level language, the description of the hardware accelerator in the same first high-level language, and the application program.
20. The computing system of claim 19 , wherein the set of acts further comprise implementing a verification phase, wherein the verification phase comprises:
identifying machine code, a simulator dynamic link library, a representation of the hardware accelerator, an electronic design automation script, and the verification test bench; and
executing a simulation process using the machine code, the simulator dynamic link library, the representation of the hardware accelerator, and the electronic design automation script, at the verification test bench.