Granted Patent B2

US 12,693,865 · App. 18/472,457 · Granted Jul 28, 2026

Inventors: Weilin Wang (Beijing, CN); Yingbing Guan (Beijing, CN); Mengchen Yang (Beijing, CN)

Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.

G06F9/3818G06F9/223G06F9/3004G06F9/30145G06F9/3017G06F9/30174G06F9/30189G06F9/455G06F9/45508

Abstract

Claims (44)

1 . A method for executing target instructions, used in a processor, comprising the steps of:

receiving an instruction;

determining whether the received instruction is a target instruction according to an operation code of the received instruction;

when the received instruction is not the target instruction, executing the received instruction in a first mode, wherein the first mode is a system management mode; and

when the received instruction is the target instruction, simulating the execution of the target instruction and checking whether the target instruction is supported according to basic decoding information of the target instruction in a second mode;

wherein the basic decoding information comprises the operation code, and is stored in an internal register.

2 . The method for executing target instructions of claim 1 , wherein the second mode includes a system management mode, when the received instruction is the target instruction, the method further comprises:

decoding the received instruction to obtain the basic decoding information;

storing the basic decoding information into the internal register;

reading the basic decoding information from the internal register; and

storing the basic decoding information into a system management memory.

3 . The method for executing target instructions of claim 1 , wherein the target instruction is not natively supported by the processor, but natively supported by other processors.

4 . The method for executing target instructions of claim 1 , wherein when the received instruction is the target instruction and an operand of the target instruction is a new architecture register, the new architecture register is simulated by a special register in the second mode.

5 . The method for executing target instructions of claim 4 , wherein when the new architecture register is a destination operand of the target instruction, the method further comprises:

after simulation execution of the target instruction is completed, storing the simulation execution result of the target instruction into the special register.

6 . The method for executing target instructions of claim 5 , wherein when the new architecture register is a destination operand of the target instruction, the method further comprises:

when exiting the second mode, doing not store the simulation execution result stored in the special register into an architecture register.

7 . The method for executing target instructions of claim 5 , further comprising:

receiving another instruction; and

when the another instruction is another target instruction and the new architecture register is the source operand of the another instruction, directly using the simulation execution result stored in the special register to simulate the execution of the another target instruction.

8 . The method for executing target instructions of claim 1 , when the received instruction is the target instruction, the method further comprising:

decoding the target instruction into a microinstruction, wherein the microinstruction comprises an emulation flag; and

setting the emulation flag of the microinstruction to a first value.

9 . The method for executing target instructions of claim 8 , wherein when the received instruction is the target instruction, the microinstruction is a special microinstruction if the received instruction needs to access memory, the method further comprises:

using the special microinstruction to check permissions of the target instruction, and generating a check result;

storing the check result into the internal register; and

simulating the execution of the target instruction according to the check result stored in the internal register.

10 . The method for executing target instructions of claim 9 , wherein the check result comprises a virtual address, a physical address, and an error code.

11 . A processor for executing target instructions, comprising:

an instruction monitoring unit, configured to receive an instruction, and to determine whether the received instruction is a target instruction according to an operation code of the received instruction; and

an internal register;

wherein when the received instruction is not the target instruction, the processor executes the received instruction in a first mode, and the first mode is a system management mode; when the received instruction is the target instruction, the processor simulates the execution of the target instruction and checks whether the target instruction is supported according to basic decoding information of the target instruction in a second mode; wherein the basic decoding information comprises the operation code, and is stored in the internal register.

12 . The processor for executing target instructions of claim 11 , further comprises:

an instruction decoding unit, wherein the second mode includes a system management mode, when the received instruction is a target instruction, the instruction decoding unit decodes the received instruction to obtain the basic decoding information;

wherein the processor reads the basic decoding information from the internal register, and stores the basic decoding information into a system management memory.

13 . The processor for executing target instructions of claim 11 , wherein the target instruction is not natively supported by the processor, but natively supported by other processors.

14 . The processor for executing target instructions of claim 11 , further comprising:

a special register, wherein when the received instruction is the target instruction, and an operand of the target instruction is a new architecture register, the new architecture register is simulated using the special register.

15 . The processor for executing target instructions of claim 14 , wherein when the new architecture register is a destination operand of the target instruction, after the processor simulates the execution of the target instruction, the processor stores the simulation execution result of the target instruction into the special register.

16 . The system for executing new instructions of claim 15 , wherein when the new architecture register is the destination operand of the target instruction, when exiting the second mode, the processor does not store the simulation execution result stored in the special register into an architecture register.

17 . The processor for executing target instructions of claim 15 , wherein the instruction monitoring unit receives another instruction; when the another instruction is another target instruction and the new architecture register is the source operand of the another instruction, the processor directly uses the simulation execution result stored in the special register to simulate the execution of the another target instruction.

18 . The processor for executing target instructions of claim 11 , wherein the instruction decoding unit decodes the received instruction into a microinstruction; wherein the microinstruction comprises an emulation flag; and the processor sets the emulation flag of the microinstruction to a first value.

19 . The processor for executing target instructions of claim 18 , wherein when the received instruction is the target instruction, the microinstruction is a special microinstruction if the received instruction needs to access memory; the processor uses the special microinstruction to check permissions of the target instruction, generates a check result, stores the check result into the internal register, and simulates the execution of the target instruction according to the check result stored in the internal register.

20 . The processor for executing target instructions of claim 19 , wherein the check result comprises a virtual address, a physical address, and an error code.

Assignments (1)

Priority Claims (2)

Continuity (2)

References Cited (157)