Semiconductor device and method

1. A method comprising:

depositing a contact etch stop layer (CESL) on a first dielectric layer;

depositing a second dielectric layer on the CESL;

etching a trench in the second dielectric layer, the CESL, and the first dielectric layer;

growing a fin in the trench;

removing the second dielectric layer;

etching a source/drain recess in the fin, the source/drain recess extending through the CESL;

growing an epitaxial source/drain region in the source/drain recess;

depositing an inter-layer dielectric (ILD) layer on the epitaxial source/drain region and the CESL;

etching an opening through the ILD layer with an isotropic etch, the isotropic etch removing portions of the ILD layer beneath the epitaxial source/drain region to expose the CESL and lower facets of the epitaxial source/drain region; and

forming a source/drain contact in the opening, the source/drain contact extending along the lower facets of the epitaxial source/drain region.

2. The method of claim 1 , wherein the etching the opening through the ILD layer comprises:

performing an anisotropic etch to form the opening, the opening exposing upper facets of the epitaxial source/drain region after the anisotropic etch, the lower facets of the epitaxial source/drain region remaining covered after the anisotropic etch; and

performing the isotropic etch to expand the opening, the opening exposing the lower facets of the epitaxial source/drain region after the isotropic etch.

3. The method of claim 2 , wherein the ILD layer comprises silicon oxide; the CESL comprises silicon nitride; the anisotropic etch is a dry etch performed with tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; and the isotropic etch is a wet etch performed with dilute hydrofluoric acid, hydrogen fluoride and ammonia, or nitrogen trifluoride and ammonia.

4. The method of claim 2 , wherein the ILD layer comprises silicon oxide; the CESL comprises silicon nitride; the anisotropic etch is a first dry etch performed with tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; the isotropic etch is a second dry etch performed with tetrafluoromethane, hexafluoro-1,3-butadiene, octafluorocyclobutane, or octafluorocyclopentene; and the second dry etch is performed at a greater pressure and with a lower bias voltage than the first dry etch.

5. The method of claim 2 , wherein the isotropic etch is performed for a duration in a range of 5 seconds to 60 seconds.

6. The method of claim 2 , wherein performing the isotropic etch widens the opening by 5% to 50%.

7. The method of claim 1 further comprising:

forming a metal-semiconductor alloy region on upper facets of the epitaxial source/drain region, the source/drain contact contacting the metal-semiconductor alloy region and a subset of the lower facets of the epitaxial source/drain region.

8. The method of claim 1 , wherein the ILD layer physically contacts the epitaxial source/drain region before etching the opening.

9. The method of claim 1 , wherein after forming the source/drain contact, a void remains beneath the epitaxial source/drain region, the void exposing a portion of the CESL.

10. A method comprising:

depositing a contact etch stop layer (CESL) on a dielectric layer;

after depositing the CESL, forming a fin protruding above the CESL;

etching a source/drain recess in the fin, the source/drain recess extending beneath a top surface of the CESL and beneath a top surface of the dielectric layer;

growing an epitaxial source/drain region in the source/drain recess;

depositing an inter-layer dielectric (ILD) on the epitaxial source/drain region and the CESL;

etching an opening through the ILD, the opening exposing an upper surface of the epitaxial source/drain region, a lower surface of the epitaxial source/drain region, and the top surface of the CESL; and

forming a contact in the opening, the contact connected to the epitaxial source/drain region.

11. The method of claim 10 , wherein etching the opening through the ILD comprises:

etching the ILD with a first etching process to expose the upper surface of the epitaxial source/drain region and a first portion of the top surface of the CESL; and

etching the ILD with a second etching process to expose the lower surface of the epitaxial source/drain region and a second portion of the top surface of the CESL, the second etching process different from the first etching process.

12. The method of claim 11 , wherein the second etching process has a greater degree of isotropy than the first etching process.

13. The method of claim 11 , wherein the second etching process widens the opening.

14. The method of claim 10 further comprising:

forming a metal-semiconductor alloy region on the upper surface of the epitaxial source/drain region, the contact contacting the metal-semiconductor alloy region and the lower surface of the epitaxial source/drain region.

15. A method comprising:

etching a trench in a contact etch stop layer (CESL) and a first dielectric layer, the CESL formed on the first dielectric layer;

growing a fin in the trench;

etching a source/drain recess in the fin, the source/drain recess extending through the CESL;

growing an epitaxial source/drain region in the source/drain recess, the CESL underlying the epitaxial source/drain region so that lower facets and upper facets of the epitaxial source/drain region are free from the CESL;

depositing an inter-layer dielectric (ILD) on the epitaxial source/drain region and the CESL;

etching an opening through the ILD to expose the upper facets of the epitaxial source/drain region, the lower facets of the epitaxial source/drain region, and the CESL; and

forming a contact in the opening, the contact connected to the epitaxial source/drain region.

16. The method of claim 15 , wherein etching the opening through the ILD comprises:

etching the ILD with an anisotropic etching process to expose the upper facets of the epitaxial source/drain region; and

etching the ILD with an isotropic etching process to expose the lower facets of the epitaxial source/drain region.

17. The method of claim 15 , wherein etching the opening through the ILD comprises:

etching the ILD with a first anisotropic etching process to expose the upper facets of the epitaxial source/drain region; and

etching the ILD with a second anisotropic etching process to expose the lower facets of the epitaxial source/drain region.

18. The method of claim 15 further comprising:

forming a metal-semiconductor alloy region on the upper facets of the epitaxial source/drain region, the contact contacting the metal-semiconductor alloy region and the lower facets of the epitaxial source/drain region.

19. The method of claim 15 , wherein the ILD physically contacts the epitaxial source/drain region before etching the opening.

20. The method of claim 15 , wherein after forming the contact, a void remains beneath the epitaxial source/drain region, the void exposing a portion of the CESL.