Stacked die integrated with package voltage regulators
An integrated circuit (IC) package is described. The IC package includes a first die having a first power delivery network on the first die. The IC package also includes a second die having a second power delivery network on the second die. The first die is stacked on the second die. The IC package further includes package voltage regulators integrated with and coupled to the first die and/or the second die within a package core of the integrated circuit package.
1. An integrated circuit (IC) package, comprising:
a package core between two substrates;
a first die having a first power delivery network on the first die, the first die located within the package core;
a second die having a second power delivery network on the second die, in which the first die is stacked on the second die, the second die located within the package core; and
a plurality of package voltage regulators integrated with and coupled to the first die and/or the second die within the package core of the integrated circuit package.
2. The IC package of claim 1 , in which a front-side surface of the first die is directly bonded to a front-side surface of the second die.
3. The IC package of claim 1 , in which a backside surface of the first die is directly bonded to a back-side surface of the second die.
4. The IC package of claim 1 , further comprising a plurality of passive devices integrated with the plurality of package voltage regulators within the package core placed around a perimeter of the first die and the second die.
5. The IC package of claim 1 ,
in which the first die includes a front-side surface and a backside surface, opposite the front-side surface, the backside surface of the first die on a front-side surface of the first power delivery network; and
in which the second die includes a front-side surface on the front-side surface of the first die and a backside surface on a front-side surface of the second power delivery network, the second power delivery network being distal from the first power delivery network.
6. The IC package of claim 5 , further comprising:
a first redistribution layer (RDL) substrate of the two substrates coupled to a backside surface of the first power delivery network; and
a second redistribution layer (RDL) substrate of the two substrates coupled to a backside surface of the second power delivery network, the second RDL substrate being distal from the first RDL substrate.
7. The IC package of claim 5 , further comprising:
a first package substrate of the two substrates coupled to a backside surface of the first power delivery network through first contact bumps; and
a second package substrate of the two substrates coupled to a backside surface of the second power delivery network through second contact bumps, the second package substrate being distal from the first package substrate.
8. The IC package of claim 7 , in which the plurality of package voltage regulators are coupled between the first package substrate and the second package substrate and coupled to the first die and/or the second die through the first contact bumps and/or the second contact bumps.
9. The IC package of claim 7 , further comprising a memory die coupled to the first package substrate through first package bumps.
10. The IC package of claim 7 , further comprising conductive core balls coupled between the first package substrate and the second package substrate.
11. The IC package of claim 1 , further comprising:
a first redistribution layer (RDL) substrate of the two substrates coupled to a front-side surface of the first die; and
a second redistribution layer (RDL) substrate of the two substrates coupled to a front-side surface of the second die, the second RDL substrate being distal from the first RDL substrate.
12. The IC package of claim 1 , further comprising:
a first package substrate of the two substrates coupled to a front-side surface of the first die through first contact bumps; and
a second package substrate of the two substrates coupled to a front-side surface of the second die through second contact bumps, the second package substrate being distal from the first package substrate.
13. A method for fabricating an integrated circuit package having a stacked die integrated with a plurality of package voltage regulators, comprising:
fabricating a first die having a first power delivery network on the first die on a first wafer;
fabricating a second die having a second power delivery network on the second die on a second wafer;
bonding the first wafer to the second wafer to form a stacked die wafer;
singulating the stacked die wafer to form the stacked die including the first power delivery network and the second power delivery network; and
placing the stacked die on a second package substrate integrated with the plurality of package voltage regulators within a package core of the integrated circuit package.
14. The method of claim 13 , in which the bonding comprises directly bonding a front-side surface of the first die to a front-side surface of the second die.
15. The method of claim 13 , in which the bonding comprises directly bonding a backside surface of the first die to a back-side surface of the second die.
16. The method of claim 13 , further comprising placing a plurality of passive devices around a perimeter of the stacked die and integrated with the plurality of package voltage regulators within the package core of the integrated circuit package.
17. The method of claim 13 , further comprising attaching a first package substrate to the stacked die and the plurality of package voltage regulators, in which the plurality of package voltage regulators and the stacked die are coupled between the first package substrate and the second package substrate.
18. An integrated circuit (IC) package, comprising:
a package core between two substrates;
a first die having a first power delivery network on the first die, the first die located within the package core;
a second die having a second power delivery network on the second die, in which the first die is stacked on the second die, the second die located within the package core; and
means for regulating voltage integrated with and coupled to the first die and/or the second die within the package core of the integrated circuit package.
19. The IC package of claim 18 , in which a front-side surface of the first die is directly bonded to a front-side surface of the second die.
20. The IC package of claim 18 , in which a backside surface of the first die is directly bonded to a back-side surface of the second die.