Semiconductor device and method for fabricating the same
A semiconductor device including: a semiconductor substrate including an active region; a plurality of conductive structures formed over the semiconductor substrate; an isolation layer filling a space between the conductive structures and having an opening that exposes the active region between the conductive structures; a pad formed in a bottom portion of the opening and in contact with the active region; a plug liner formed conformally over a sidewall of the opening and exposing the pad; and a contact plug formed over the pad inside the opening.
1. A semiconductor device, comprising:
a semiconductor substrate including an active region;
a plurality of conductive structures formed over the semiconductor substrate;
an isolation layer filling a space between the conductive structures and having an opening that exposes the active region between the conductive structures;
a pad formed in a bottom portion of the opening and in contact with the active region;
a plug liner formed conformally over a sidewall of the opening and exposing the pad; and
a contact plug formed over the pad inside the opening,
wherein a bottom portion of the opening is positioned at a lower level than an upper surface of the active region.
2. The semiconductor device of claim 1 , wherein the pad includes an epitaxial layer.
3. The semiconductor device of claim 1 , further comprising:
an oxide spacer between the sidewall of the opening and the plug liner.
4. The semiconductor device of claim 1 , wherein an upper surface of the isolation layer is at the same level as an upper surface of the conductive structure.
5. The semiconductor device of claim 1 , wherein the plug liner includes polysilicon.
6. A semiconductor device, comprising:
a semiconductor substrate including an active region;
a plurality of bit line structures formed over the semiconductor substrate;
an isolation layer filling a space between the bit line structures and having an opening that exposes the active region between the bit line structures;
a pad formed in a bottom portion of the opening and in contact with the active region;
a first spacer formed over conformally on a sidewall of the opening and exposing the pad;
a plug liner formed to cover a lower portion of the first spacer;
a second spacer formed over the plug liner to cover an upper portion of the first spacer; and
a contact plug formed over the pad inside of the opening.
7. The semiconductor device of claim 6 , wherein the contact plug includes:
a first plug having an upper surface at the same level as the plug liner; and
a second plug formed over the first plug and having an upper surface at the same level as the second spacer.
8. The semiconductor device of claim 6 , wherein the pad includes an epitaxial layer.
9. The semiconductor device of claim 6 , wherein the first spacer includes silicon oxide, and the second spacer includes silicon nitride.
10. The semiconductor device of claim 6 , wherein the plug liner includes polysilicon.
11. The semiconductor device of claim 6 , further comprising:
a word line buried in the semiconductor substrate;
first source/drain regions and second source/drain regions formed in the semiconductor substrate on both sides of the word line;
a bit line contact plug formed over the first source/drain regions; and
a bit line over the bit line contact plug,
wherein the pad is coupled to the second source/drain regions.