Semiconductor device with asymmetric gate structure

1. A semiconductor device, comprising:

a substrate;

a channel layer, positioned above the substrate;

a barrier layer, positioned above the channel layer, the barrier layer and the channel layer being configured to form two-dimensional electron gas (2DEG), and the two-dimensional electron gas being formed in the channel layer along an interface between the channel layer and the barrier layer;

a low voltage device including a first source contact and a first drain contact, positioned above the barrier layer;

a first doped group III-V layer, positioned above the barrier layer and between the first drain contact and the first source contact, the first doped group III-V layer having a first sidewall adjacent to the first source contact and a second sidewall adjacent to the first drain contact, and in a direction substantially parallel to the interface, a shortest distance between the first sidewall and the first source contact being L 1 , and a shortest distance between the second sidewall and the first drain contact being L 2 ; and

a first gate electrode, positioned above the doped group III-V layer and configured to form a Schottky junction with the doped group III-V layer, the first gate electrode having a third sidewall adjacent to the first source contact and a fourth sidewall adjacent to the first drain contact, and in the direction substantially parallel to the interface, a shortest distance between the third sidewall and the first source contact being L 3 , and a shortest distance between the fourth sidewall and the first drain contact being L 4 , and

wherein L 1 +L 3 ≠L 2 +L 4 ;

and a high voltage device including:

a second source contact and a second drain contact, positioned above the barrier layer;

a second doped group III-V layer, positioned above the barrier layer and between the second drain contact and the second source contact;

a second gate electrode, positioned above the second doped group III-V layer and configured to form a Schottky junction with the second doped group III-V layer, the second gate electrode having a fifth sidewall adjacent to the second source contact and a sixth sidewall adjacent to the second drain contact;

a first field plate positioned between the second gate electrode and the second drain contact;

a second field plate positioned above the first field plate and between the second gate electrode and the second drain contact;

wherein a profile of the fifth sidewall and a profile of the sixth sidewall are substantially in non-specular symmetry with respect to a geometric center of the second doped group III-V layer and

an isolation region positioned between the low voltage device and the high voltage device.

2. The semiconductor device according to claim 1 , wherein the surface roughness of the third sidewall is substantially different from the surface roughness of the fourth sidewall.

3. The semiconductor device according to claim 1 , wherein (L 4 −L 2 )/(L 3 −L 1 )>1.1.

4. The semiconductor device according to claim 1 , wherein L 2 /L 1 >1.

5. The semiconductor device according to claim 1 , wherein (L 3 −L 1 )/(L 4 −L 2 )>1.1.

6. The semiconductor device according to claim 1 , further comprising a first passivation layer positioned at least partially above the barrier layer and at least partially above the doped group III-V layer.

7. The semiconductor device according to claim 1 , wherein the channel layer comprises a first group III-V material, the barrier layer comprises a second group III-V material, and the bandgap of the second group III-V material is greater than the bandgap of the first group III-V material.

8. A semiconductor device, comprising:

a substrate;

a channel layer, positioned above the substrate;

a barrier layer, positioned above the channel layer, the barrier layer being configured to form two-dimensional electron gas (2DEG), and the two-dimensional electron gas being formed in the channel layer along an interface between the channel layer and the barrier layer;

a source contact and a drain contact, positioned above the barrier layer;

a doped group III-V layer, positioned above the barrier layer and between the drain contact and the source contact; and

a gate electrode, positioned above the doped group III-V layer and configured to form a Schottky junction with the doped group III-V layer, the gate electrode having a third sidewall adjacent to the source contact and a fourth sidewall adjacent to the drain contact;

a first passivation layer positioned at least partially above the barrier layer and at least partially above the doped group III-V layer;

a first field plate positioned at least partially above the first passivation layer and between the gate electrode and the drain contact;

a second field plate positioned above and at least partially overlapping the first field plate and between the gate electrode and the drain contact;

a third field plate positioned above the first and second field plates and at least partially overlapping the first and second field plates;

wherein a profile of the third sidewall and a profile of the fourth sidewall are substantially in non-specular symmetry with respect to a geometric center of the doped group III-V layer.

9. The semiconductor device according to claim 8 , further comprising a buffer layer positioned between the substrate and the channel layer.

10. The semiconductor device according to claim 9 , wherein the buffer layer comprises a superlattice structure.

11. The semiconductor device according to claim 8 , further comprising a conductor structure, the conductor structure being in direct contact with the gate electrode.

12. The semiconductor device according to claim 11 , wherein the conductor structure comprises a plurality of conductor material layers.