Semiconductor device
A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.
1. A semiconductor device, comprising:
a substrate having a central region and a peripheral region surrounding the central region;
an integrated circuit structure on the central region of the substrate; and
at least one first structure on the peripheral region of the substrate and surrounding the central region of the substrate,
wherein:
a portion of the at least one first structure includes:
a first fin structure defined by a device isolation region in the substrate and protruding from the substrate;
a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region;
a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering a lower surface and side surfaces of the first gate conductive layer, and first gate spacer layers on both side walls of the first gate conductive layer; and
a first insulating structure covering the first dielectric layer and the first gate structure,
the first fin structure includes a first fin line portion having a linear shape and extending in a first direction,
the first gate conductive layer of the first gate structure includes a first gate line portion having a linear shape and extending in the first direction,
the first fin line portion has a first width in a second direction perpendicular to the first direction, and
the first gate line portion has a second width in the second direction, the second width being narrower than the first width.
2. The semiconductor device as claimed in claim 1 , wherein:
the first fin structure includes a first lower semiconductor region, and first to third silicon layers and first to third silicon-germanium layers alternately stacked on the first lower semiconductor region,
the first silicon layer is between the first silicon-germanium layer and the second silicon-germanium layer,
the second silicon layer is between the second silicon-germanium layer and the third silicon-germanium layer, and
the third silicon layer is on an upper surface of the third silicon-germanium layer.
3. The semiconductor device as claimed in claim 2 , wherein the first width of the first fin line portion is a minimum width of the third silicon layer in the second direction.
4. The semiconductor device as claimed in claim 1 , wherein:
the first fin structure is a single fin protruding further in a vertical direction than the upper surface of the device isolation region, and
the first width of the first fin line portion is a minimum width of the first fin structure on a cross-sectional surface taken in the second direction.
5. The semiconductor device as claimed in claim 1 , wherein the first dielectric layer has a thickness greater than a thickness of the first gate dielectric layer.
6. The semiconductor device as claimed in claim 1 , further comprising:
a first wiring layer in the first insulating structure on the first gate structure; and
a first contact structure between the first gate conductive layer and the first wiring layer,
wherein a width of the first contact structure in the second direction is narrower than the first width of the first fin line portion.
7. The semiconductor device as claimed in claim 1 , wherein:
the integrated circuit structure includes:
circuit fin patterns defined by the device isolation region of the substrate and extending in the first direction, the circuit fin patterns including a plurality of channel layers spaced apart from each other in a vertical direction;
a circuit gate electrode intersecting the circuit fin patterns and extending in the second direction; and
source/drain regions on the circuit fin patterns on both sides of the circuit gate electrode, and
the first width of the first fin line portion is greater than a width of each of the plurality of channel layers of the circuit fin patterns in the second direction.
8. The semiconductor device as claimed in claim 1 , further comprising at least one second structure on the peripheral region of the substrate,
wherein the at least one second structure includes:
a second fin structure defined by the device isolation region in the substrate, protruding from the substrate, and extending in the first direction;
a second dielectric layer covering the second fin structure and the device isolation region;
a second insulating structure covering the second dielectric layer;
a lower contact structure in the second insulating structure on the second fin structure, connected to the second fin structure, and having a width greater than a width of the second fin structure;
an upper contact structure connected to the lower contact structure on the lower contact structure; and
a second wiring layer connected to the upper contact structure on the upper contact structure.
9. The semiconductor device as claimed in claim 8 , wherein:
the peripheral region of the substrate includes a guard-ring region surrounding the central region and a blocking region surrounding the guard-ring region,
the at least one second structure includes a plurality of the second structures on each of the guard-ring region and the blocking region, and
the at least one first structure includes a plurality of the first structures on the blocking region.
10. The semiconductor device as claimed in claim 1 , wherein, in a plan view:
the first fin structure has a serrated shape, and
the first gate conductive layer has a serrated shape on the first fin structure.
11. The semiconductor device as claimed in claim 1 , wherein:
the first fin structure includes a plurality of semiconductor layers, and
at least a portion of the first gate conductive layer is between the plurality of semiconductor layers.
12. The semiconductor device as claimed in claim 1 , wherein the upper surface of the first fin structure includes bent portions.
13. A semiconductor device, comprising:
a substrate having a central region and a peripheral region surrounding the central region;
an integrated circuit structure on the central region of the substrate; and
a first structure surrounding the central region on the peripheral region of the substrate,
wherein:
a portion of the first structure includes:
a first fin structure protruding further than a device isolation region disposed in the substrate and extending in a first direction;
a first dielectric layer covering the device isolation region and the first fin structure; and
a first gate conductive layer extending in the first direction on the first fin structure,
the first fin structure has a first side surface and a second side surface opposing each other in a second direction perpendicular to the first direction in which the first fin structure and the first gate conductive layer extend,
the first gate conductive layer has a third side surface and a fourth side surface opposing each other in the second direction,
the first dielectric layer covers the first side surface and the second side surface of the first fin structure, and
a distance between the first side surface and the second side surface in the second direction is greater than a distance between the third side surface and the fourth side surface in the second direction.
14. The semiconductor device as claimed in claim 13 , wherein the first side surface of the first fin structure includes a first portion covered by the first dielectric layer and a second portion covered by the device isolation region.
15. The semiconductor device as claimed in claim 13 , wherein:
the first fin structure includes a first lower semiconductor region, and a plurality of first layers and a plurality of second layers alternately stacked on the first lower semiconductor region,
the plurality of first layers include a first silicon-germanium layer, a second silicon-germanium layer, and a third silicon-germanium layer spaced apart from one another in a vertical direction, and
the plurality of second layers include a first silicon layer, a second silicon layer, and a third silicon layer spaced apart from one another in the vertical direction.
16. The semiconductor device as claimed in claim 13 , further comprising a first gate dielectric layer covering the third and fourth side surfaces of the first gate conductive layer, having a thickness less than a thickness of the first dielectric layer, and including a material having a dielectric constant higher than a dielectric constant of the first dielectric layer.
17. The semiconductor device as claimed in claim 13 , wherein a portion of at least one of the first and second side surfaces is side by side with a portion of at least one of the third and fourth side surfaces.
18. A semiconductor device, comprising:
a substrate having a central region and a peripheral region surrounding the central region;
a plurality of transistors on the central region of the substrate, the plurality of transistors including circuit fin patterns, a circuit gate structure, and source/drain regions; and
a plurality of first structures on the peripheral region of the substrate,
wherein:
a portion of each first structure of the plurality of first structures includes:
a first fin structure having a linear shape, defined by a device isolation region in the substrate, and extending in a first direction, and
a first gate conductive layer having a linear shape and extending in the first direction on the first fin structure, and
a first distance between opposing side surfaces of the first fin structures adjacent to each other is less than a second distance between opposing side surfaces of the first gate conductive layers adjacent to each other in a second direction perpendicular to the first direction.
19. The semiconductor device as claimed in claim 18 , wherein a width of the first fin structure in the second direction is greater than a width of each of the circuit fin patterns in the second direction.
20. The semiconductor device as claimed in claim 19 , wherein:
the circuit fin patterns include a plurality of channel layers spaced apart from each other in a vertical direction,
the circuit gate structure includes a circuit gate conductive layer between the plurality of channel layers and on the plurality of channel layers,
the first fin structure includes a first lower semiconductor region and a plurality of first layers and a plurality of second layers alternately stacked on the first lower semiconductor region,
the plurality of first layers include a first silicon-germanium layer, a second silicon-germanium layer, and a third silicon-germanium layer spaced apart from one another in the vertical direction, and
the plurality of second layers include a first silicon layer, a second silicon layer, and a third silicon layer spaced apart from one another in the vertical direction.