Cool electron erasing in thin-film storage transistors

1. A storage transistor having a tunnel dielectric layer, a charge-trapping layer, and a barrier layer, all of which being provided between a channel region and a gate electrode, wherein (i) the barrier layer is provided between the tunnel dielectric layer and the charge-trapping layer; (ii) the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer; and (iii) the barrier layer has a conduction band offset less than the conduction band offset of the charge-trapping layer.

2. The storage transistor of claim 1 , wherein the conduction band offset of the charge-trapping layer is between −1.0 eV and 2.3 eV.

3. The storage transistor of claim 1 , wherein the charge-trapping layer comprises a material selected from the group consisting of: hafnium oxide (HfO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 4 ), lanthanum oxide (La 2 O 3 ) tantalum oxide (Ta 2 O 5 ), cerium oxide (CeO 2 ), titanium oxide (TiO 2 ), strontium titanium oxide (SrTiO 3 ), silicon nanodots, ruthenium nanodots, platinum nanodots and cobalt nanodots.

4. The storage transistor of claim 1 , wherein the conduction band offset of the charge-trapping layer is greater than the energy difference between a charge-trapping site in the charge-trapping layer and the conduction band edge of the charge-trapping layer.

5. The storage transistor of claim 1 , wherein the direct-tunneling provides a current exceeding 1.0 amps/cm 2 .

6. The storage transistor of claim 1 , wherein the tunnel dielectric layer has a thickness that allow programming and erasing operations to be accomplished predominantly by direct tunneling.

7. The storage transistor of claim 1 , wherein the tunnel dielectric layer comprises one or more of: silicon oxide, silicon nitride and silicon oxynitride.

8. The storage transistor of claim 1 using tunnel dielectric layer comprises stoichiometric silicon nitride.

9. The storage transistor of claim 7 , wherein the tunnel dielectric layer comprises silicon oxide that is formed using an ozone step.

10. The storage transistor of claim 7 , wherein the tunnel dielectric layer is formed using a pulsed ozone step, an H 2 anneal, a NH 3 anneal, a rapid thermal anneal, or any combination thereof.

11. The storage transistor of claim 7 , further comprising in the tunnel dielectric layer a layer of aluminum oxide.

12. The storage transistor of claim 11 , wherein the aluminum oxide layer has a thickness that is not greater than 1 nm.

13. The storage transistor of claim 1 wherein, when a voltage substantially less than the programming voltage is applied across the channel region and the gate electrode, electrons tunnel into the charge-trapping layer by Fowler-Nordheim tunneling or a modified Fowler-Nordheim tunneling.

14. The storage transistor of claim 13 , wherein the applied voltage corresponds to a programming inhibit voltage or an erase inhibit voltage and wherein electrons tunneling into the charge trapping layer provides a current density less than 0.1 amps/cm 2 .

15. The storage transistor of claim 1 , having an average endurance exceeding 10 11 programming-erase cycles.

16. The storage transistor of claim 1 , wherein the barrier layer comprises a material having a conduction band offset between −1.00 eV and 1.5 eV.

17. The storage transistor of claim 14 , wherein the barrier layer comprises a material selected from the group consisting of: hafnium oxide (HfO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 4 ), tantalum oxide (Ta 2 O 5 ), cerium oxide (CeO 2 ), titanium oxide (TiO 2 ), silicon-rich silicon nitride (SiN:Si), strontium titanium oxide (SrTiO 3 ), silicon nanodots, ruthenium nanodots, platinum nanodots and cobalt nanodots.

18. The storage transistor of claim 14 , wherein the tunnel dielectric layer comprises silicon oxide, the barrier layer comprises tantalum oxide, and the charge-trapping layer comprises silicon-rich silicon nitride.

19. The storage transistor of claim 14 , wherein the tunnel dielectric layer comprises silicon oxide, the barrier layer comprises cerium oxide, and the charge-trapping layer comprises silicon-rich silicon nitride.

20. The storage transistor of claim 14 , wherein the tunnel dielectric layer comprises silicon nitride, the barrier layer comprises cerium oxide, and the charge-trapping layer comprises silicon-rich silicon nitride.

21. The storage transistor of claim 14 , wherein the tunnel dielectric layer comprises silicon oxide, the barrier layer comprises zirconium oxide, and the charge-trapping layer comprises silicon-rich silicon nitride.

22. The storage transistor of claim 14 wherein, when a voltage substantially less than the programming voltage is applied across the channel region and the gate electrode, electrons tunnel into the charge-trapping layer by Fowler-Nordheim turnneling or a modified Fowler-Nordheim tunneling.

23. The storage transistor of claim 1 , further comprising a blocking dielectric layer between the charge-trapping layer and the gate electrode.

24. The storage transistor of claim 23 , the blocking dielectric layer further comprises a layer of aluminum oxide.

25. The storage transistor of claim 24 , wherein the aluminum oxide layer in the blocking dielectric layer has a thickness between 2 nm and 5 nm.

26. The storage transistor of claim 1 , wherein the storage transistor is a quasi-volatile memory transistor.

27. The storage transistor of claim 26 , wherein storage transistor is one of a plurality of thin-film storage transistors formed in a NOR memory string.

28. The storage transistor of claim 27 , wherein the NOR memory string is one of a plurality of NOR memory strings in a 3-dimensional array.

29. The storage transistor of claim 1 , wherein the storage transistor is a quasi-volatile memory transistor.

30. The storage transistor of claim 29 , wherein storage transistor is one of a plurality of thin-film storage transistors formed in a NOR memory string.

31. The storage transistor of claim 30 , wherein the NOR memory string is one of a plurality of NOR memory strings in a 3-dimensional array.