IP Library Granted Patent US 11,515,902
Granted Patent B2
US 11,515,902 · App. 17/514,849 · Granted Nov 29, 2022

Method and apparatus for phase error compensation having tolerance to cyclic slip

Inventors: Sang Rok Moon (Daejeon, KR); Minkyu Sung (Daejeon, KR); Eon-sang Kim (Daejeon, KR); Won Kyoung Lee (Daejeon, KR); Seung-Hyun Cho (Daejeon, KR)
Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
H04B1/12H04B17/29
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Quick Facts
Patent No.
US 11,515,902
App. No.
17/514,849
Granted
Nov 29, 2022
Kind
B2
Abstract

Disclosed is a method and apparatus for phase error compensation having tolerance to a cyclic slip. The method includes determining first phase error candidates based on symbol phases of a first block of a received signal, determining an initial estimation error according to the first phase error candidates, determining second phase error candidates based on symbol phases of a second block of the received signal, determining a final estimation error according to the initial estimation error and the second phase error candidates, and compensating for a phase of the received signal according to the final estimation error.

Claims (30)

1. A method for compensating for a phase error of a signal, the method comprising:

determining first phase error candidates based on symbol phases of a first block of a received signal;

determining an initial estimation error according to the first phase error candidates;

determining second phase error candidates based on symbol phases of a second block of the received signal;

determining a final estimation error according to the initial estimation error and the second phase error candidates; and

compensating for a phase of the received signal according to the final estimation error.

2. The method of claim 1 , wherein:

the first block comprises N reception symbols among reception symbols included in the received signal, where N is an integer, and

the second block comprises M reception symbols among the reception symbols included in the first block, where M is an integer less than N.

3. The method of claim 1 , wherein the determining of the first phase error candidates comprises determining the first phase error candidates according to phase differences between an average value of the symbol phases of the first block and points included in a constellation.

4. The method of claim 1 , wherein the determining of the initial estimation error comprises determining a smallest first phase error candidate of the first phase error candidates as the initial estimation error.

5. The method of claim 1 , wherein the determining of the second phase error candidates comprises determining the second phase error candidates according to phase differences between an average value of the symbol phases of the second block and points included in a constellation.

6. The method of claim 1 , wherein the determining of the final estimation error comprises comparing each of the second phase error candidates with the initial estimation error, and determining a second phase error candidate having a smallest difference from the initial estimation error, of the second phase error candidates, as the final estimation error.

7. The method of claim 1 , wherein the compensating comprises compensating for the phase of the received signal by applying a reciprocal of the final estimation error to reception symbols included in the second block.

8. Anon-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1 .

9. An apparatus for compensating for a phase error of a signal, the apparatus comprising:

a processor, and a memory having instructions stored thereon executed by the processor to perform:

a first phase error candidate determiner configured to determine first phase error candidates based on symbol phases of a first block of a received signal;

an initial estimation error determiner configured to determine an initial estimation error according to the first phase error candidates;

a second phase error candidate determiner configured to determine second phase error candidates based on symbol phases of a second block of the received signal;

a final estimation error determiner configured to determine a final estimation error according to the initial estimation error and the second phase error candidates; and

a phase compensator configured to compensate for a phase of the received signal according to the final estimation error.

10. The apparatus of claim 9 , wherein:

the first block comprises N reception symbols among reception symbols included in the received signal, where N is an integer, and

the second block comprises M reception symbols among the reception symbols included in the first block, where M is an integer less than N.

11. The apparatus of claim 9 , wherein the first phase error candidate determiner is further configured to determine the first phase error candidates according to phase differences between an average value of the symbol phases of the first block and points included in a constellation.

12. The apparatus of claim 9 , wherein the initial estimation error determiner is further configured to determine a smallest first phase error candidate of the first phase error candidates as the initial estimation error.

13. The apparatus of claim 9 , wherein the second phase error candidate determiner is further configured to determine the second phase error candidates according to phase differences between an average value of the symbol phases of the second block and points included in a constellation.

14. The apparatus of claim 9 , wherein the final estimation error determiner is further configured to compare each of the second phase error candidates with the initial estimation error, and determine a second phase error candidate having a smallest difference from the initial estimation error, of the second phase error candidates, as the final estimation error.

15. The apparatus of claim 9 , wherein the phase compensator is further configured to compensate for the phase of the received signal by applying a reciprocal of the final estimation error to reception symbols included in the second block.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2021
From: MOON, SANG ROK; SUNG, MINKYU; KIM, EON-SANG; LEE, WON KYOUNG; CHO, SEUNG-HYUN
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 057966/0563 →
Priority Claims (1)
KR 10-2021-0016217 · Feb 4, 2021 · national
Continuity (1)
Related Publication 20220247439A1 · Aug 4, 2022
Cited By (1)
US 12,640,652