Apparatus and method to achieve fast-fault detection on power semiconductor devices
An apparatus and methods to operate the same to provide fast fault-detection on power semiconductor devices such as power transistors are disclosed. In some embodiment, a desaturation based fault-detection circuit for a power transistor is provided. The fault-detection circuit has an adaptable blanking time and a disconnect switch in the blanking mechanism that allow for quick enabling of fault-detection mechanisms to achieve fast fault detection times on power semiconductor devices.
1. A fault-detection circuit for a power transistor, the fault-detection circuit comprising:
a sense input terminal configured to detect a collector-to-emitter voltage of the power transistor;
a gate sense terminal configured to detect a gate voltage of the power transistor;
a protection comparator having a comparator input and a comparator output;
a switch coupled between the sense input terminal and the comparator input, the switch controllable to be open when the power transistor transitions from an off state to an on state until the gate voltage crosses a pre-determined threshold, wherein
the fault-detection circuit is configured to generate an output signal at the comparator output indicative of a fault based on the measured collector-to-emitter voltage.
2. The fault-detection circuit of claim 1 , wherein the power transistor has a first terminal and a second terminal, and wherein the sense input terminal is configured to be coupled to a voltage node that is connected to the first terminal, the voltage node having a voltage relative to the second terminal, and wherein
an amplitude of the voltage of the voltage node relative to the second terminal is larger than zero during a period when the switch is open.
3. The fault-detection circuit of claim 2 , further comprising a capacitor coupled between the first terminal and the second terminal, and wherein the voltage is a voltage across the capacitor.
4. The fault-detection circuit of claim 1 , wherein the pre-determined threshold is a gate plateau voltage during a transition of the power transistor from an off state to an on state.
5. The fault-detection circuit of claim 1 , further comprising a gate sense comparator configured to compare the gate voltage with the pre-determined threshold, and to generate a gate sense signal indicating that the gate voltage crosses the pre-determined threshold.
6. The fault-detection circuit of claim 5 , further comprising control logic configured to receive the gate sense signal, and to control the switch to open upon receiving the gate sense signal.
7. The fault-detection circuit of claim 1 , wherein the protection comparator is configured to compare a voltage at the comparator input with a desaturation voltage threshold, and to generate the output signal when the voltage at the comparator input crosses the desaturation voltage threshold.
8. A fault-detection circuit for a power transistor, the fault-detection circuit comprising:
a protection comparator having a comparator input and a comparator output, wherein the comparator input is configured to detect a collector-to-emitter voltage of the power transistor;
a gate sense terminal configured to measure a gate voltage of the power transistor;
a switch coupled between the comparator output and a reference voltage, the switch controlled to be closed when the power transistor transitions from an off state to an on state until the gate voltage crosses a pre-determined threshold, wherein
the fault-detection circuit is configured to generate an output signal at the comparator output indicative of a fault based on the measured collector-to-emitter voltage.
9. The fault-detection circuit of claim 8 , wherein the power transistor has a first terminal and a second terminal, and wherein the comparator input is configured to be coupled to a voltage node that is connected to the first terminal, the voltage node having a voltage relative to the second terminal, and wherein
an amplitude of the voltage of the voltage node relative to the second terminal is larger than zero during a period when the switch is open.
10. The fault-detection circuit of claim 9 , further comprising a capacitor coupled between the first terminal and the second terminal, and wherein the voltage is a voltage across the capacitor.
11. The fault-detection circuit of claim 8 , wherein the pre-determined threshold is a gate plateau voltage during a transition of the power transistor from an off state to an on state.
12. The fault-detection circuit of claim 8 , further comprising a gate sense comparator configured to compare the gate voltage with the pre-determined threshold, and to generate a gate sense signal indicating that the gate voltage crosses the pre-determined threshold.
13. The fault-detection circuit of claim 12 , further comprising a control logic configured to receive the gate sense signal, and to control the switch to open upon receiving the gate sense signal.
14. The fault-detection circuit of claim 8 , wherein the protection comparator is configured to compare a voltage at the comparator input with a desaturation voltage threshold, and to generate the output signal when the voltage at the comparator input crosses the desaturation voltage threshold.
15. A method for detecting fault condition for a power transistor having a gate, a first terminal and a second terminal, the method comprising:
turning on the power transistor from an off state;
determining whether a gate voltage of the power transistor crosses a pre-determined threshold;
in response to a determination that the gate voltage crosses the pre-determined threshold, coupling a sense input terminal to a voltage node that is connected to the first terminal by closing a switch coupled between the sense input terminal and the voltage node;
determining whether a collector-to-emitter voltage of the power transistor at the sense input terminal crosses a pre-determined threshold; and
in response to a determination that the measured collector-to-emitter voltage crosses the pre-determined threshold, determining a fault.
16. The method of claim 15 , further comprising:
maintaining a voltage of the voltage node to be larger than zero during a period when the switch is open.
17. The method of claim 16 , further comprising a capacitor coupled between the first terminal and the second terminal, and wherein the voltage is a voltage across the capacitor.
18. The method of claim 15 , wherein the pre-determined threshold is a gate plateau voltage during a transition of the power transistor from an off state to an on state.
19. The method of claim 15 , wherein turning on the power transistor comprises:
providing a gate drive output signal to the gate to turn on the power transistor.
20. The method of claim 19 , further comprising:
opening the switch when the gate drive output signal is provided to the gate.