Managing capacity reduction when downshifting multi-level memory cells
A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell; sending a message to a host system indicating a reduced capacity of the set of memory devices; receiving from the host system a message to continue at the reduced capacity; and updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device.
1. A system comprising:
a set of memory devices; and
a processing device, operatively coupled with the set of memory devices, to perform operations comprising:
detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell;
sending a message to a host system indicating a reduced capacity of the set of memory devices;
receiving from the host system a message to continue at the reduced capacity;
updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device;
sending a message to the host system indicating that the set of memory devices comprises data in excess of the reduced capacity;
receiving, from the host system, an indication of a storage location to store the data in excess of the reduced capacity, wherein the storage location is in a main memory of the host system; and
providing the data in excess of the reduced capacity to the storage location.
2. The system of claim 1 , wherein the memory device comprises multi-level cells and wherein reducing the quantity of bits stored per memory cell comprises downshifting a quad-level cell to a triple-level cell.
3. The system of claim 1 , wherein detecting the failure comprises:
calculating a reliability measurement based on an ability of the memory device to store the multiple bits per memory cell; and
determining a failure exists responsive to comparing the reliability measurement and a predetermined threshold value.
4. The system of claim 1 , further comprising:
detecting a second failure of the memory device, the second failure being based on an inability of the memory device to store the reduced quantity of bits per memory cell; and
updating the set of memory devices to further reduce the quantity of bits stored per memory cell of the memory device.
5. The system of claim 1 , wherein sending the message comprises:
sending a first message to the host system to indicate the failure, wherein the first message is an Asynchronous Event Notification (AEN) message; and
sending a second message to the host system to indicate a set of storage units affected by the failure.
6. The system of claim 1 , the processing device is a memory controller of a solid state drive.
7. A method comprising:
detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell;
sending a message to a host system indicating a reduced capacity of the set of memory devices;
receiving, by a processing device, from the host system a message to continue at the reduced capacity;
updating, by the processing device, the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device;
sending a message to the host system indicating that the set of memory devices comprises data in excess of the reduced capacity;
receiving, from the host system, an indication of a storage location to store the data in excess of the reduced capacity, wherein the storage location is in a main memory of the host system; and
providing the data in excess of the reduced capacity to the storage location.
8. The method of claim 7 , wherein the memory device comprises multi-level cells and wherein reducing the quantity of bits stored per memory cell comprises downshifting a quad-level cell to a triple-level cell.
9. The method of claim 7 , wherein detecting the failure comprises:
calculating a reliability measurement based on an ability of the memory device to store the multiple bits per memory cell; and
determining a failure exists responsive to comparing the reliability measurement and a predetermined threshold value.
10. The method of claim 7 , further comprising:
detecting a second failure of the memory device, the second failure being based on an inability of the memory device to store the reduced quantity of bits per memory cell; and
updating the set of memory devices to further reduce the quantity of bits stored per memory cell of the memory device.
11. The method of claim 7 , wherein sending the message comprises:
sending a first message to the host system to indicate the failure, wherein the first message is an Asynchronous Event Notification (AEN) message; and
sending a second message to the host system to indicate a set of storage units affected by the failure.
12. The method of claim 7 , wherein the processing device is a memory controller of a solid state drive.
13. A non-transitory computer-readable medium storing instructions, which when executed by a processing device, cause the processing device to perform operations comprising:
detecting a plurality of failures of a memory device, wherein the memory device stores multiple bits per memory cell;
sending a message to a host system after each of the plurality of failures of indicate a reduced capacity of the set of memory devices;
receiving from the host system a message to continue at the reduced capacity after each of the plurality of failures;
updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device after each of the plurality of failures;
sending a message to the host system indicating that the set of memory devices comprises data in excess of the reduced capacity;
receiving, from the host system, an indication of a storage location to store the data in excess of the reduced capacity, wherein the storage location is in a main memory of the host system; and
providing the data in excess of the reduced capacity to the storage location.
14. The non-transitory computer-readable medium of claim 13 , wherein the memory device comprises multi-level cells and wherein reducing the quantity of bits stored per memory cell after one of the plurality of failures comprises downshifting a quad-level cell to a triple-level cell.
15. The non-transitory computer-readable medium of claim 13 , wherein detecting the plurality of failures comprises:
calculating a reliability measurement based on an ability of the memory device to store the multiple bits per memory cell; and
determining one of the plurality of failures exists responsive to comparing the reliability measurement and a predetermined threshold value.
16. The non-transitory computer-readable medium of claim 13 , wherein sending the message comprises:
sending a first message to the host system to indicate the failure, wherein the first message is an Asynchronous Event Notification (AEN) message; and
sending a second message to the host system to indicate a set of storage units affected by the failure.
17. The non-transitory computer-readable medium of claim 13 , wherein the processing device is a memory controller of the solid state drive.