Display device

1. A display device comprising:

a substrate including a display area and a non-display area around the display area;

a transistor disposed on the substrate;

an insulating layer disposed on the transistor;

a power voltage line disposed on the insulating layer, the power voltage line transferring a power voltage;

a data line disposed on the insulating layer, the data line transferring a data voltage;

an auxiliary wire disposed between the substrate and the power voltage line in the display area, the auxiliary wire including a portion overlapping the power voltage line and, a portion overlapping the data line in a plan view, the auxiliary wire being electrically connected to the power voltage line and in contact with the substrate; and

a lower pattern overlapping an active pattern of the transistor, wherein the auxiliary wire is disposed on a same layer as the lower pattern and the auxiliary wire is an electrically separate node from the lower pattern.

2. The display device of claim 1 , wherein

the power voltage line is a driving voltage line that transfers a driving voltage or a common voltage line that transfers a common voltage.

3. The display device of claim 2 , wherein

the driving voltage line is connected to a source region or a drain region of the transistor through a contact hole formed in the insulating layer, and to the auxiliary wire through another contact hole formed in the insulating layer.

4. The display device of claim 2 , further comprising

a pixel electrode electrically connected to the transistor, wherein

the auxiliary wire includes a portion overlapping the pixel electrode in the plan view.

5. The display device of claim 4 , wherein

the auxiliary wire includes a portion overlapping the driving voltage line and a portion overlapping the common voltage line in the plan view.

6. The display device of claim 2 , wherein

the power voltage line is a driving voltage line connected to the auxiliary wire through a contact hole formed in at least the insulating layer.

7. The display device of claim 1 , wherein

the lower pattern is electrically connected to a source region or a drain region of the transistor.

8. The display device of claim 1 , further comprising

a buffer layer disposed between the transistor and the auxiliary wire, wherein

the buffer layer is a multilayer including at least two layers.

9. The display device of claim 8 , wherein

the power voltage line is connected to the auxiliary wire through a contact hole formed in the insulating layer and the buffer layer.

10. The display device of claim 1 , wherein

the auxiliary wire is disposed in a same layer as the lower pattern, and

the auxiliary wire is spaced apart from the lower pattern.