Semiconductor device with fuse and anti-fuse structures and method for forming the same
The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure.
1. A semiconductor device, comprising:
a first dielectric layer disposed over a semiconductor substrate;
a first electrode disposed over the first dielectric layer;
a fuse link disposed over the first electrode;
a second electrode disposed over the fuse link;
a third electrode disposed adjacent to the first electrode; and
a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode, wherein the first electrode, the fuse link, and the second electrode form a fuse structure, and wherein the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure;
wherein the first electrode has a first width, the fuse link has a second width, and the second electrode has a third width, and
wherein the third width is greater than the first width, and the first width is greater than the second width.
2. The semiconductor device of claim 1 , wherein the third electrode is in direct contact with the first dielectric layer.
3. The semiconductor device of claim 1 , wherein the third electrode is covered by the second dielectric layer.
4. The semiconductor device of claim 1 , wherein the first electrode has a rounded profile in a cross-sectional view.
5. The semiconductor device of claim 1 , wherein the first electrode and the fuse link are surrounded by the second dielectric layer.
6. The semiconductor device of claim 1 , wherein a lower portion of the second electrode is surrounded by the second dielectric layer.
7. A semiconductor device, comprising:
a first dielectric layer disposed over a semiconductor substrate;
a first conductive line and a second conductive line disposed over the first dielectric layer and extending parallel to each other;
a second dielectric layer disposed between the first conductive line and the second conductive line, wherein the first conductive line and the second conductive line are covered by the second dielectric layer;
a third dielectric layer disposed over the second dielectric layer, wherein the third dielectric layer has a different etch selectivity than the second dielectric layer;
a first electrode disposed between the first conductive line and the second conductive line, wherein the first electrode has a rounded profile, and the first electrode is separated from the first dielectric layer by the second dielectric layer; and
a second electrode disposed over the first electrode, wherein the second electrode extends from the second dielectric layer to the third dielectric layer.
8. The semiconductor device of claim 7 , wherein the first electrode, the first conductive line, and a portion of the second dielectric layer sandwiched between the first electrode and the first conductive line form an anti-fuse structure.
9. The semiconductor device of claim 8 , further comprising:
a fuse link disposed between the first electrode and the second electrode, wherein the first electrode, the second electrode, and the fuse link form a fuse structure.
10. The semiconductor device of claim 7 , wherein the first electrode is in direct contact with the first conductive line, and wherein the first electrode and the first conductive line form a fuse structure.
11. The semiconductor device of claim 10 , further comprising:
a dielectric portion disposed between the first electrode and the second electrode, wherein the first electrode, the second electrode, and the dielectric portion form an anti-fuse structure.
12. The semiconductor device of claim 11 , wherein the dielectric portion has a first width, the second electrode has a second width, and the second width is greater than the first width.
13. The semiconductor device of claim 7 , further comprising:
a third conductive line disposed over the first dielectric layer and extending parallel to the first conductive line, wherein the first conductive line is between the second conductive line and the third conductive line, and wherein the first conductive line and the third conductive line have an air gap therebetween, the air gap is sealed by the third dielectric layer.
14. The semiconductor device of claim 13 , wherein a sidewall of the first conductive line and a sidewall of the third conductive line are exposed by the air gap.