Package structure and fabrication methods
The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.
1. A package structure, comprising:
a frame, comprising:
a silicon substrate having a first side opposite a second side;
a quadrilateral cavity formed therein and extending through the substrate from the first side to the second side; and
a plurality of cylindrical vias formed therein and extending through the substrate from the first side to the second side, the plurality of vias arranged in one or more rows on each side of the cavity;
an active die disposed within the cavity;
a first plurality of electrical interconnections, each of the first plurality of electrical interconnections disposed within one of the plurality of vias; and
a dielectric layer formed over the first side and the second side, the dielectric layer disposed over each side of the active die and forming an intermediate layer between each of the first plurality of electrical interconnections and a sidewall of a corresponding via that the first electrical interconnection is disposed within.
2. The package structure of claim 1 , wherein the substrate comprises crystalline silicon.
3. The package structure of claim 2 , wherein the substrate comprises monocrystalline p-type or n-type silicon.
4. The package structure of claim 1 , wherein the substrate has a thickness between about 110 μm and about 200 μm.
5. The package structure of claim 1 , wherein the dielectric layer has a thickness less than about 150 μm between the active die and a sidewall of the cavity.
6. The package structure of claim 1 , the intermediate layer has a thickness less than about 150 μm between each of the first plurality of electrical interconnections and a sidewall of the corresponding via that the first electrical interconnection is disposed within.
7. The package structure of claim 1 , further comprising an oxide layer formed over the first side and the second side of the substrate.
8. The package structure of claim 7 , wherein the oxide layer has a thickness between about 300 nm and about 2 μm.
9. The package structure of claim 1 , wherein the dielectric layer comprises a laminated epoxy resin having a ceramic filler.
10. The package structure of claim 9 , wherein the ceramic filler comprises at least one of silica, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, zirconium silicate, wollastonite, beryllium oxide, cerium dioxide, boron nitride, calcium copper titanium oxide, magnesium oxide, titanium dioxide, and zinc oxide.
11. The package structure of claim 1 , further comprising a second plurality of electrical interconnections formed through the dielectric layer and in electrical contact with the active die.
12. The package structure of claim 1 , wherein a minimum pitch between each of the plurality of vias is between about 70 μm and about 200 μm.
13. The package structure of claim 1 , further comprising a molybdenum layer and a copper layer formed within each of the plurality of vias and disposed between the electrical interconnection and the dielectric layer in the via.
14. A package structure, comprising:
a frame, comprising:
a silicon substrate having a first side opposite a second side;
a quadrilateral cavity formed therein and extending through the substrate from the first side to the second side;
a plurality of cylindrical vias formed therein and extending through the substrate from the first side to the second side, the plurality of vias arranged in one or more rows on each side of the cavity; and
an oxide layer formed over the first side, the second side, and sidewalls of the cavity and sidewalls of each of the plurality of vias;
at least one active multipurpose die disposed within the cavity;
a first plurality of electrical interconnections, each of the first plurality of electrical interconnections disposed within one of the plurality of vias and extending at least from the first side to the second side;
a dielectric layer formed over the first side and the second side, the dielectric layer disposed over each side of the at least one active multipurpose die and forming an intermediate layer between each of the first plurality of electrical interconnections and the sidewall of a corresponding via the first electrical interconnection is disposed within, the dielectric layer comprising a laminated epoxy resin filled with ceramic fillers; and
a second plurality of electrical interconnections formed through the dielectric layer and in electrical communication with the at least one active multipurpose die.
15. The package structure of claim 14 , wherein the substrate comprises a monocrystalline p-type or n-type silicon solar substrate.
16. The package structure of claim 14 , wherein the dielectric layer has a thickness less than about 150 μm between the at least one active multipurpose die and the sidewalls of the cavity.
17. The package structure of claim 14 , the intermediate layer has a thickness less than about 150 μm between each of the first plurality of electrical interconnections and the sidewall of the corresponding via that the first electrical interconnection is disposed within.
18. The package structure of claim 14 , further comprising:
a third plurality of conductive interconnections partially formed through the dielectric layer, the third plurality of interconnections forming a redistribution layer over the first side or the second side.
19. A stacked package structure, comprising:
a first frame, comprising:
a first silicon substrate having a first side opposite a second side;
a first cavity formed therein and extending through the first substrate from the first side to the second side; and
a first plurality of vias formed therein and extending through the first substrate from the first side to the second side;
a second frame stacked over the first frame, comprising:
a second silicon substrate having a first side opposite a side;
a second cavity formed therein and extending through the second substrate from the first side to the second side; and
a second plurality of vias formed therein and extending through the second substrate from the first side to the second side;
an active die disposed within each of the first cavity and the second cavity;
a plurality of electrical interconnections, each of the plurality of electrical interconnections disposed within one of the first or second pluralities of vias; and
a dielectric layer in contact with the first frame and the second frame and separating each of the first frame and the second frame, the dielectric layer disposed over each side of the active dies and forming an intermediate layer between each of the plurality of electrical interconnections and a sidewall of a corresponding via the electrical interconnection is disposed within.
20. The stacked package structure of claim 19 , further comprising an oxide layer formed over each of the first substrate and the second substrate.