System architecture, structure and method for hybrid random access memory in a system-on-chip
A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
1. A hybrid random access memory in a system-on-chip, comprising:
a semiconductor substrate with a magnetoresistive random access memory (MRAM) region and a resistive random-access memory (ReRAM) region;
a first dielectric layer on said semiconductor substrate, wherein said first dielectric layer is a first inter-metal layer (IMD 1 );
multiple ReRAM cells in said first dielectric layer on said ReRAM region, wherein each of said ReRAM cells comprises:
a first bottom electrode, wherein said first bottom electrode is formed in a dielectric capping layer under said first dielectric layer, and top surfaces of said first bottom electrode and said dielectric capping layer are flush, and said first bottom electrode physically touches a contact below, and said contact is directly connected to an active area of underlying said semiconductor substrate;
a first top electrode above said first bottom electrode;
a variable resistive layer between said first bottom electrode and said first top electrode; and
spacers on sidewalls of said variable resistive layer and said first top electrode;
a second dielectric layer above said first dielectric layer; and
multiple MRAM cells in said second dielectric layer on said MRAM region, wherein each of said MRAM cells comprises:
a second bottom electrode connected directly to a via below, and said via is further connected to an underlying metal layer;
a magnetic tunnel junction (MTJ) component on said second bottom electrode;
a second top electrode on said magnetic tunnel junction component; and
a capping layer covering said second top electrode and said magnetic tunnel junction component.
2. The hybrid random access memory in a system-on-chip according to claim 1 , wherein said variable resistive layer is a multilayer structure with a tantalum oxide layer, a tantalum pentaoxide layer and an iridium layer.
3. The hybrid random access memory in a system-on-chip according to claim 1 , wherein said first top electrode of each of said ReRAM cells is connected to an overlying metal layer through a via.
4. The hybrid random access memory in a system-on-chip according to claim 1 , wherein said magnetic tunnel junction component comprises a seed layer, a pinned layer, a reference layer, a tunnel barrier layer and a free layer.