Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices
Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
1. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
an upper semiconductor body vertically over and isolated from a lower semiconductor body;
a first gate structure for controlling the upper semiconductor body, the first gate structure having a first conductivity type; and
a second gate structure for controlling the lower semiconductor body, the second gate structure having a second conductivity type, the second conductivity type of the second gate structure opposite the first conductivity type of the first gate structure, wherein the second gate structure is separate and distinct from the first gate structure.
2. The computing device of claim 1 , further comprising:
a memory coupled to the board.
3. The computing device of claim 1 , further comprising:
a communication chip coupled to the board.
4. The computing device of claim 1 , further comprising:
a camera coupled to the board.
5. The computing device of claim 1 , further comprising:
an antenna coupled to the board.
6. The computing device of claim 1 , wherein the component is a packaged integrated circuit die.
7. The computing device of claim 1 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
8. The computing device of claim 1 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.
9. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
an upper semiconductor body vertically over and isolated from a lower semiconductor body;
a first gate structure for controlling the upper semiconductor body, the first gate structure having a first conductivity type; and
a second gate structure for controlling the lower semiconductor body, the second gate structure having a second conductivity type, the second conductivity type of the second gate structure the same as the first conductivity type of the first gate structure, wherein the second gate structure is separate and distinct from the first gate structure.
10. The computing device of claim 9 , further comprising:
a memory coupled to the board.
11. The computing device of claim 9 , further comprising:
a communication chip coupled to the board.
12. The computing device of claim 9 , wherein the component is a packaged integrated circuit die.
13. The computing device of claim 9 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.
14. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a semiconductor fin separated vertically into an upper region and a lower region;
a first plurality of gate structures for controlling the upper region of the semiconductor fin; and
a second plurality of gate structures for controlling the lower region of the semiconductor fin, the second plurality of gate structures having a conductivity type opposite the conductivity type of the first plurality of gate structures, wherein the second plurality of gate structures is separate and distinct from the first plurality of gate structures.
15. The computing device of claim 14 , further comprising:
a memory coupled to the board.
16. The computing device of claim 14 , further comprising:
a communication chip coupled to the board.
17. The computing device of claim 14 , wherein the component is a packaged integrated circuit die.
18. The computing device of claim 14 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.
19. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a semiconductor fin separated vertically into an upper region and a lower region;
a first plurality of gate structures for controlling the upper region of the semiconductor fin; and
a second plurality of gate structures for controlling the lower region of the semiconductor fin, the second plurality of gate structures having a same conductivity type as the conductivity type of the first plurality of gate structures, wherein the second plurality of gate structures is separate and distinct from the first plurality of gate structures.
20. The computing device of claim 19 , further comprising:
a memory coupled to the board.
21. The computing device of claim 19 , further comprising:
a communication chip coupled to the board.
22. The computing device of claim 19 , wherein the component is a packaged integrated circuit die.
23. The computing device of claim 19 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.