IP Library Granted Patent US 11,522,102
Granted Patent B2
US 11,522,102 · App. 17/149,814 · Granted Dec 6, 2022

Semiconductor device

Inventors: Huan-Yu Lai (Hsinchu, TW); Li-Chi Peng (Hsinchu, TW)
Assignee: EPISTAR CORPORATION
H01L33/145H01L33/0062H01L33/04H01L33/06H01L33/14H01L33/30H01L33/305H01L33/32H01L33/325
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,522,102
App. No.
17/149,814
Granted
Dec 6, 2022
Kind
B2
Abstract

A semiconductor device is provided. The semiconductor device includes a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; an active region between the second semiconductor layer and the first semiconductor layer; an electron blocking structure between the active region and the second semiconductor layer; a first Group III-V semiconductor layer between the active region and the electron blocking structure; and a second Group III-V semiconductor layer between the electron blocking structure and the second semiconductor layer; wherein the first Group III-V semiconductor layer and the second Group III-V semiconductor layer each includes indium, aluminum and gallium, the first Group III-V semiconductor layer has a first indium content, the second Group III-V semiconductor layer has a second indium content, and the second indium content is less than the first indium content.

Claims (26)

1. A semiconductor device, comprising:

a first semiconductor layer;

a second semiconductor layer on the first semiconductor layer;

an active region between the second semiconductor layer and the first semiconductor layer;

an electron blocking structure between the active region and the second semiconductor layer;

a first Group III-V semiconductor layer between the active region and the electron blocking structure; and

a second Group III-V semiconductor layer between the electron blocking structure and the second semiconductor layer; wherein the first Group III-V semiconductor layer and the second Group III-V semiconductor layer each comprises indium, aluminum and gallium elements, wherein the first Group III-V semiconductor layer has a first indium content, the second Group III-V semiconductor layer has a second indium content, and the second indium content is less than the first indium content.

2. The semiconductor device according to claim 1 , wherein the first Group III-V semiconductor layer has a first aluminum content, the second Group III-V semiconductor layer has a second aluminum content, and the second aluminum content is different from the first aluminum content.

3. The semiconductor device according to claim 2 , wherein the second aluminum content is less than the first aluminum content.

4. The semiconductor device according to claim 1 , wherein the electron blocking structure and the first Group III-V semiconductor layer sandwich an intermediate layer.

5. The semiconductor device according to claim 1 , wherein the electron blocking structure is in direct contact with the first Group III-V semiconductor layer.

6. The semiconductor device according to claim 1 , wherein the second Group III-V semiconductor layer has an energy gap different form an energy gap of the first Group III-V semiconductor layer.

7. The semiconductor device according to claim 1 , wherein the electron blocking structure comprises a third semiconductor layer having an energy gap, the active region comprises alternating well layers and barrier layers, and the energy gap of the third semiconductor layer is greater than an energy gap of one of the barrier layers.

8. The semiconductor device according to claim 7 , wherein the energy gap of the third semiconductor layer is greater than both of an energy gap of the first Group III-V semiconductor layer and an energy gap of the second Group III-V semiconductor layer.

9. The semiconductor device according to claim 1 , wherein the electron blocking structure and the second Group III-V semiconductor layer each comprises a dopant having a concentration, the concentration of the dopant of the second Group III-V semiconductor layer is less than the concentration of the dopant of the electron blocking structure.

10. The semiconductor device according to claim 9 , wherein the first Group III-V semiconductor layer comprises a dopant having a concentration, wherein the concentration of the dopant of the first Group III-V semiconductor layer is between the concentration of the dopant of the electron blocking structure and the concentration of the dopant of the second Group III-V semiconductor layer.

11. The semiconductor device according to claim 9 , wherein the dopant of the electron blocking structure comprises Mg.

12. The semiconductor device according to claim 9 , wherein the concentration of the dopant of the electron blocking structure is not less than 5×10 18 /cm 3 .

13. The semiconductor device according to claim 9 , wherein the concentration of the dopant of the first Group III-V semiconductor layer is not less than 5×10 18 /cm 3 .

14. The semiconductor device according to claim 1 , wherein the electron blocking structure comprises alternating third semiconductor layers and fourth semiconductor layers.

15. The semiconductor device according to claim 14 , wherein one of the fourth semiconductor layers includes a fourth indium content, the fourth indium content is greater than the second indium content of the second Group III-V semiconductor layer.

16. The semiconductor device according to claim 14 , wherein one of the third semiconductor layers and one of the fourth semiconductor layers adjacent to the one of the third semiconductor layers are considered as a pair, a pair number of the third semiconductor layers and the fourth semiconductor layers is not less than 3.

17. The semiconductor device according to claim 14 , wherein a thickness of the electron blocking structure is between 15 nm and 60 nm both inclusive.

18. The semiconductor device according to claim 14 , wherein a thickness of one of the third semiconductor layers is less than a thickness of one of the fourth semiconductor layers.

19. The semiconductor device according to claim 18 , wherein the thickness of one of the third semiconductor layers is between 1.5 nm and 5 nm both inclusive, and the thickness of one of the fourth semiconductor layers is between 2 nm and 5 nm both inclusive.

20. The semiconductor device according to claim 1 , wherein the active region comprises an upper surface facing the first Group III-V semiconductor layer, a first distance between the first Group III-V semiconductor layer and the upper surface of the active region is not more than 15 nm.

Assignments (2)
CHANGE OF NAME Recorded Feb 13, 2026
From: EPISTAR CORPORATION
To: ENNOSTAR CORPORATION
Reel/Frame 074858/0856 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2021
From: LAI, HUAN-YU; PENG, LI-CHI
To: EPISTAR CORPORATION
Reel/Frame 054929/0531 →
Continuity (2)
Continuation 15929614 · May 13, 2020
Related Publication 20210359158A1 · Nov 18, 2021