Processing apparatus and inference system

1. A processing apparatus, comprising:

a recurrent neural network circuit that receives M first signals and outputs N second signals, M being an integer of 2 or more, N being an integer of 2 or more; and

a control circuit that adjusts a plurality of coefficients that are set to the recurrent neural network circuit according to a first delay time period from timing for applying the M first signals until timing for firing the N second signals.

2. The processing apparatus according to claim 1 , wherein

the M first signals each represent a binary value and the N second signals each represent a binary value,

the recurrent neural network circuit includes N product-sum operation circuits corresponding to the N second signals,

with respect to each of the N product-sum operation circuits, M coefficients corresponding to the M first signals are set,

if an ith first signal, for which i is an integer of 1 or more and M or less, among the M first signals is applied to the recurrent neural network circuit and the recurrent neural network circuit causes a jth second signal, for which j is an integer of 1 or more and N or less, among the N second signals to be fired, the control circuit adjusts, according to the first delay time period, a relative relationship between a target coefficient among the plurality of coefficients that are set to the recurrent neural network circuit and a coefficient group other than the target coefficient among the plurality of coefficients set to the recurrent neural network circuit, and

the target coefficient is a coefficient that is multiplied by the ith first signal among the M coefficients set to the product-sum operation circuit that outputs the jth second signal among the N product-sum operation circuits included in the recurrent neural network circuit.

3. The processing apparatus according to claim 2 , wherein

the application timing is timing at which the ith first signal among the M first signals is applied to the recurrent neural network circuit, and

the firing timing is timing, after the application timing, at which the jth second signal among the N second signals is initially fired.

4. The processing apparatus according to claim 2 , wherein

the N product-sum operation circuits each include a comparator that receives a voltage according to a value obtained by performing a product-sum operation with respect to the M first signals and the M coefficients that are set, binarizes the received voltage, and outputs a binarized signal as a corresponding second signal among the N second signals.

5. The processing apparatus according to claim 4 , wherein, if the first delay time period is shorter than a preset threshold value, the control circuit relatively reduces the target coefficient and relatively increases the coefficient group other than the target coefficient.

6. The processing apparatus according to claim 5 , wherein, as the first delay time period shortens, the control circuit increases a relative reduction amount of the target coefficient and increases a relative increase amount of the coefficient group other than the target coefficient.

7. The processing apparatus according to claim 1 , wherein the recurrent neural network circuit includes a first operation circuit that receives the M first signals and executes a neural network operation that outputs the N second signals, and a switching circuit, and

upon receipt of input data, the switching circuit

supplies the M first signals according to the input data to the first operation circuit, and

after supplying the M first signals according to the input data to the first operation circuit, supplies the N second signals to the first operation circuit as the M first signals.

8. The processing apparatus according to claim 7 , wherein

M=N.

9. The processing apparatus according to claim 1 , further comprising:

a coefficient memory that stores therein a plurality of digital coefficient values that correspond to the plurality of coefficients set to the recurrent neural network circuit, wherein

the control circuit

adjusts the plurality of digital coefficient values stored in the coefficient memory according to the first delay time period, and

changes the plurality of coefficients set to the recurrent neural network circuit on the basis of the plurality of digital coefficient values stored in the coefficient memory.

10. The processing apparatus according to claim 9 ,

wherein the plurality of coefficients set to the recurrent neural network circuit are each represented by a first gradation number, and

the plurality of digital coefficient values are each represented by a second gradation number that is greater than the first gradation number,

the control circuit transforms each of the plurality of digital coefficient values to the first gradation number, and

on the basis of the plurality of digital coefficient values represented by the first gradation number, the control circuit changes the plurality of coefficients set to the recurrent neural network circuit.

11. An inference system, comprising:

a recurrent neural network circuit that receives M input signals and outputs N intermediate signals, M being an integer of 2 or more, N being an integer of 2 or more;

an inference neural network circuit that receives the N intermediate signals and outputs L output signals, L being an integer of 2 or more; and

a control circuit that adjusts a plurality of coefficients set to the recurrent neural network circuit and a plurality of coefficients set to the inference neural network circuit, wherein

the control circuit adjusts a plurality of coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.

12. The inference system according to claim 11 , wherein

the M input signals each represent a binary value, the N intermediate signals each represent a binary value, and the L output signals each represent a binary value,

the recurrent neural network circuit includes N product-sum operation circuits corresponding to the N intermediate signals,

with respect to each of the N product-sum operation circuits, M coefficients corresponding to the M input signals are set,

if an ith input signal, for which i is an integer of 1 or more and M or less, among the M input signals is applied to the recurrent neural network circuit, the control circuit adjusts, according to the total delay time period, a relative relationship between an input coefficient group set to the recurrent neural network circuit and a coefficient group other than the input coefficient group set to the recurrent neural network circuit, and

the input coefficient group is a coefficient group that is multiplied by the ith input signal among the plurality of coefficients set to the recurrent neural network circuit.

13. The inference system according to claim 12 , wherein

the N product-sum operation circuits each include a comparator, which receives a voltage according to a value obtained by performing a product-sum operation with respect to the M input signals and the set M coefficients, binarizes the received voltage, and outputs a binarized signal as the corresponding intermediate signal among the N intermediate signals.

14. The inference system according to claim 13 , wherein,

if the total delay time period is longer than a preset threshold value, the control circuit relatively increases the input coefficient group and relatively reduces the coefficient group other than the input coefficient group.

15. The inference system according to claim 14 , wherein,

as the total delay time period increases, the control circuit increases a relative increase amount of the input coefficient group and increases a relative reduction amount of the coefficient group other than the input coefficient group.

16. The inference system according to claim 12 , wherein,

if the ith input signal is applied to the recurrent neural network circuit and the recurrent neural network circuit causes a jth intermediate signal, for which j is an integer of 1 or more and N or less, among the N intermediate signals to be fired, the control circuit adjusts, according to the first delay time period from timing for applying the M input signals until timing for firing the N intermediate signals, a relative relationship between a target coefficient among a plurality of coefficients set to the recurrent neural network circuit and a coefficient group other than the target coefficient, and

the target coefficient is a coefficient that is multiplied by the ith input signal among the M coefficients set to a product-sum operation circuit that outputs the jth output signal among the N product-sum operation circuits included in the recurrent neural network circuit.

17. The inference system according to claim 12 , wherein

the inference neural network circuit includes L product-sum operation circuits corresponding to the L output signals,

with respect to each of the L product-sum operation circuits, N coefficients corresponding to the N intermediate signals are set,

if the Mth input signal according to training data is applied to the recurrent neural network circuit and the inference neural network circuit causes a kth output signal, for which k is an integer of 1 or more and L or less and which is indicated in teaching data among the L output signals, to be fired,

the control circuit adjusts, according to a second delay time period from timing for applying the M input signals or timing for applying the N intermediate signals until timing for firing the L output signals, a relative relationship between an output coefficient group among the plurality of coefficients that are set to the inference neural network circuit and a coefficient group other than the output coefficient group among the plurality of coefficients set to the inference neural network circuit, and

the output coefficient group is the N coefficients set to the product-sum operation circuit that outputs the kth output signal among the L product-sum operation circuits included in the inference neural network circuit.

18. The inference system according to claim 17 , wherein,

if the second delay time period is longer than a preset threshold value, the control circuit relatively increases the output coefficient group and relatively reduces the coefficient group other than the output coefficient group, and

as the second delay time period increases, the control circuit increases a relative increase amount of the output coefficient group and increases a relative reduction amount of the coefficient group other than the output coefficient group.

19. The inference system according to claim 17 , wherein,

if the M input signals according to the training data are supplied to the recurrent neural network circuit, the control circuit adjusts a plurality of coefficients set to the inference neural network circuit so that the output signal indicated in the teaching data among the L output signals is fired.

20. The inference system according to claim 11 , wherein

the inference neural network circuit includes

a second operation circuit that receives the N intermediate signals and executes a neural network operation that outputs L signals, and an output circuit that generates the L output signals corresponding to the L signals that are output from the second operation circuit, and

the output circuit causes each of the L output signals to be fired according to a firing pattern for a corresponding signal among the L signals.