Pixel driving circuit, driving method thereof, display panel and display device

1. A pixel driving circuit, comprising: a pulse-width adjustment module, an amplitude adjustment module and a light-emitting element,

wherein the pulse-width adjustment module is electrically connected to a sweep signal terminal and comprises a pulse-width drive transistor, and the pulse-width drive transistor is configured to supply a sweep signal supplied from the sweep signal terminal to the amplitude adjustment module;

wherein the amplitude adjustment module is configured to control a light emission duration of the light-emitting element according to the sweep signal;

wherein the pulse-width adjustment module further comprises a pulse-width data-writing unit, and the pulse-width data-writing unit is configured to supply a pulse-width data signal to a gate of the pulse-width drive transistor; and

wherein the pulse-width adjustment module further comprises a pulse-width storage unit, and the pulse-width storage unit is configured to store the pulse-width data signal.

2. The pixel driving circuit according to claim 1 , wherein the pulse-width data-writing unit comprises a first transistor, and wherein a first terminal of the first transistor is electrically connected to a pulse-width data signal terminal, a second terminal of the first transistor is electrically connected to the gate of the pulse-width drive transistor, and a gate of the first transistor is electrically connected to a first pulse-width data-writing scanning-signal terminal;

or,

wherein the pulse-width data-writing unit comprises:

a second transistor, wherein a first terminal of the second transistor is electrically connected to a pulse-width data signal terminal, a second terminal of the second transistor is electrically connected to a first terminal of the pulse-width drive transistor, and a gate of the second transistor is electrically connected to a second pulse-width data-writing scanning-signal terminal; and

a third transistor, wherein a first terminal of the third transistor is electrically connected to a second terminal of the pulse-width drive transistor, a second terminal of the third transistor is electrically connected to the gate of the pulse-width drive transistor, and a gate of the third transistor is electrically connected to a third pulse-width data-writing scanning-signal terminal;

or,

wherein the pulse-width data-writing unit comprises:

a fourth transistor, wherein a first terminal of the fourth transistor is electrically connected to a pulse-width data signal terminal, and a gate of the fourth transistor is electrically connected to a fourth pulse-width data-writing scanning-signal terminal; and

a first capacitor, wherein a first plate of the first capacitor is electrically connected to a second terminal of the fourth transistor, and a second plate of the first capacitor is electrically connected to the gate of the pulse-width drive transistor.

3. The pixel driving circuit according to claim 1 , wherein the pulse-width storage unit comprises a pulse-width storage capacitor, and a first plate of the pulse-width storage capacitor is electrically connected to a first voltage terminal;

wherein the first voltage terminal is configured to supply a constant voltage;

wherein the amplitude adjustment module is electrically connected to a first power terminal; and

wherein the first voltage terminal is electrically connected to the first power terminal.

4. The pixel driving circuit according to claim 1 , wherein the pulse-width storage unit comprises a pulse-width storage capacitor, and a first plate of the pulse-width storage capacitor is electrically connected to a second voltage terminal; and

wherein voltages supplied from the second voltage terminal comprise a first voltage value and a second voltage value that are different from each other.

5. The pixel driving circuit according to claim 1 , wherein the pulse-width adjustment module further comprises a data voltage boosting unit, and the data voltage boosting unit is configured to boost the pulse-width data signal stored in the pulse-width storage unit.

6. The pixel driving circuit according to claim 5 , wherein the data voltage boosting unit comprises a feedthrough capacitor, and a first plate of the feedthrough capacitor is electrically connected to a third voltage terminal; and

wherein voltages supplied from the third voltage terminal comprise a third voltage value and a fourth voltage value that are different from each other.

7. The pixel driving circuit according to claim 6 , wherein:

the pulse-width data-writing unit comprises a first transistor, wherein a first terminal of the first transistor is electrically connected to a pulse-width data signal terminal, a second terminal of the first transistor is electrically connected to the gate of the pulse-width drive transistor, a gate of the first transistor is electrically connected to a first pulse-width data-writing scanning-signal terminal, and the third voltage terminal is electrically connected to the first pulse-width data-writing scanning-signal terminal; or

the pulse-width data-writing unit comprises a second transistor and a third transistor, wherein a first terminal of the second transistor is electrically connected to the pulse-width data signal terminal, a second terminal of the second transistor is electrically connected to a first terminal of the pulse-width drive transistor, a gate of the second transistor is electrically connected to a second pulse-width data-writing scanning-signal terminal, a first terminal of the third transistor is electrically connected to a second terminal of the pulse-width drive transistor, a second terminal of the third transistor is electrically connected to the gate of the pulse-width drive transistor, a gate of the third transistor is electrically connected to a third pulse-width data-writing scanning-signal terminal, and the third voltage terminal is electrically connected to the third pulse-width data-writing scanning-signal terminal; or

the pulse-width data-writing unit comprises a fourth transistor and a first capacitor, wherein a first terminal of the fourth transistor is electrically connected to the pulse-width data signal terminal, a gate of the fourth transistor is electrically connected to a fourth pulse-width data-writing scanning-signal terminal, a first plate of the first capacitor is electrically connected to a second terminal of the fourth transistor, a second plate of the first capacitor is electrically connected to the gate of the pulse-width drive transistor, and the third voltage terminal is electrically connected to the fourth pulse-width data-writing scanning-signal terminal.

8. The pixel driving circuit according to claim 5 , wherein the pulse-width storage unit comprises a pulse-width storage capacitor, the data voltage boosting unit comprises a feedthrough capacitor, and a capacitance of the feedthrough capacitor is smaller than a capacitance of the pulse-width storage capacitor.

9. The pixel driving circuit according to claim 1 , wherein the pulse-width data signal is less than or equal to the sweep signal.

10. The pixel driving circuit according to claim 1 , wherein the pulse-width adjustment module further comprises a pulse-width adjustment unit,

the pulse-width adjustment unit comprises a pulse-width adjustment transistor, wherein a first terminal of the pulse-width adjustment transistor is electrically connected to the sweep signal terminal, a second terminal of the pulse-width adjustment transistor is electrically connected to a first terminal of the pulse-width drive transistor, and a gate of the pulse-width adjustment transistor is electrically connected to a pulse-width light emission signal terminal; and

wherein the pulse-width adjustment module further comprises a pulse-width light emission control unit and a pulse-width reset unit;

the pulse-width light emission control unit comprises a pulse-width light emission control transistor, wherein a first terminal of the pulse-width light emission control transistor is electrically connected to a second terminal of the pulse-width drive transistor, a second terminal of the pulse-width light emission control transistor is electrically connected to the amplitude adjustment module, and a gate of the pulse-width light emission control transistor is electrically connected to the pulse-width light emission signal terminal; and

the pulse-width reset unit comprises a pulse-width reset transistor, wherein a first terminal of the pulse-width reset transistor is electrically connected to a reference voltage terminal, a second terminal of the pulse-width reset transistor is electrically connected to a gate of the pulse-width drive transistor, and a gate of the pulse-width reset transistor is electrically connected to a pulse-width reset scanning-signal terminal.

11. The pixel driving circuit according to claim 1 , wherein the amplitude adjustment module comprises an amplitude drive transistor, the amplitude drive transistor is configured to drive the light-emitting element; and

the pulse-width drive transistor is configured to supply the sweep signal supplied from the sweep signal terminal to a gate of the amplitude drive transistor;

or,

wherein the amplitude adjustment module comprises an amplitude drive transistor and an amplitude light emission control unit;

the amplitude drive transistor is configured to drive the light-emitting element;

the amplitude light emission control unit is configured to control conducting a driving path for the amplitude drive transistor to drive the light-emitting element; and

the pulse-width drive transistor is configured to supply the sweep signal supplied from the sweep signal terminal to a control terminal of the amplitude light emission control unit.

12. The pixel driving circuit according to claim 1 , wherein the amplitude adjustment module comprises an amplitude drive transistor, an amplitude data-writing unit, an amplitude storage unit, an amplitude adjustment unit, an amplitude light emission control unit and an amplitude reset unit,

wherein the amplitude data-writing unit comprises one of the following:

a fifth transistor, wherein a first terminal of the fifth transistor is electrically connected to an amplitude data signal terminal, a second terminal of the fifth transistor is electrically connected to a gate of the amplitude drive transistor, and a gate of the fifth transistor is electrically connected to a first amplitude data-writing scanning-signal terminal;

a sixth transistor and a seventh transistor, wherein a first terminal of the sixth transistor is electrically connected to the amplitude data signal terminal, a second terminal of the sixth transistor is electrically connected to a first terminal of the amplitude drive transistor, and a gate of the sixth transistor is electrically connected to a second amplitude data-writing scanning-signal terminal, and wherein a first terminal of the seventh transistor is electrically connected to a second terminal of the amplitude drive transistor, a second terminal of the seventh transistor is electrically connected to the gate of the amplitude drive transistor, and a gate of the seventh transistor is electrically connected to a third amplitude data-writing scanning-signal terminal; or,

an eighth transistor and a second capacitor, wherein a first terminal of the eighth transistor is electrically connected to the amplitude data signal terminal, and a gate of the eighth transistor is electrically connected to a fourth amplitude data-writing scanning-signal terminal; and wherein a first plate of the second capacitor is electrically connected to a second terminal of the eighth transistor, and a second plate of the second capacitor is electrically connected to the gate of the amplitude drive transistor;

wherein the amplitude storage unit comprises an amplitude storage capacitor, a first plate of the amplitude storage capacitor is electrically connected to a first power terminal, and a second plate of the amplitude storage capacitor is electrically connected to the gate of the amplitude drive transistor;

wherein the amplitude adjustment unit comprises an amplitude adjustment transistor, a first terminal of the amplitude adjustment transistor is electrically connected to the first power terminal, a second terminal of the amplitude adjustment transistor is electrically connected to the first terminal of the amplitude drive transistor, and a gate of the amplitude adjustment transistor is electrically connected to an amplitude light emission signal terminal;

wherein the amplitude light emission control unit comprises an amplitude light emission control transistor, a first terminal of the amplitude light emission control transistor is electrically connected to the second terminal of the amplitude drive transistor, a second terminal of the amplitude light emission control transistor is electrically connected to the light-emitting element, and a gate of the amplitude light emission control transistor is electrically connected to the amplitude light emission signal terminal; and

wherein the amplitude reset unit comprises an amplitude reset transistor, a first terminal of the amplitude reset transistor is electrically connected to a reference voltage terminal, a second terminal of the amplitude reset transistor is electrically connected to the gate of the amplitude drive transistor, and a gate of the amplitude reset transistor is electrically connected to an amplitude reset scanning-signal terminal.

13. A display panel comprising the pixel driving circuit according to claim 1 .

14. A display device comprising the display panel according to claim 13 .

15. A pixel driving circuit comprising a pulse-width adjustment module, an amplitude adjustment module and a light-emitting element,

wherein the pulse-width adjustment module comprises a pulse-width drive transistor and a pulse-width adjustment unit, the pulse-width drive transistor comprises a first terminal, a second terminal and a control terminal, a control terminal of the pulse-width adjustment unit is electrically connected to a pulse-width light emission signal terminal, a first terminal of the pulse-width adjustment unit is electrically connected to a sweep signal terminal, and a second terminal of the pulse-width adjustment unit is electrically connected to the first terminal of the pulse-width drive transistor; and

wherein an input terminal of the amplitude adjustment module is electrically connected to an output terminal of the pulse-width adjustment module, and an output terminal of the amplitude adjustment module is electrically connected to the light-emitting element.

16. A driving method of a pixel driving circuit, wherein

the pixel driving circuit comprises a pulse-width adjustment module, an amplitude adjustment module and a light-emitting element;

the pulse-width adjustment module is electrically connected to a sweep signal terminal and comprises a pulse-width drive transistor; and

a working process of the pixel driving circuit comprises a light emission stage;

wherein the driving method comprises:

in the light emission stage, supplying, by the pulse-width drive transistor, a sweep signal supplied from the sweep signal terminal to the amplitude adjustment module, and controlling, by the amplitude adjustment module, a light emission duration of the light-emitting element according to the sweep signal; and

wherein

the pulse-width adjustment module further comprises a pulse-width storage capacitor, a first plate of the pulse-width storage capacitor is electrically connected to a second voltage terminal, and voltages supplied from the second voltage terminal comprise a first voltage value and a second voltage value that are different from each other; and

the working process of the pixel driving circuit further comprises a data-writing stage; and

the driving method further comprises:

in the data-writing stage, supplying a voltage having the first voltage value from the second voltage terminal; and

in the light emission stage, supplying a voltage having the second voltage value from the second voltage terminal;

or,

the pulse-width adjustment module further comprises a pulse-width storage capacitor and a feedthrough capacitor, the pulse-width storage capacitor is configured to store a pulse-width data signal, and the feedthrough capacitor is configured to boost the pulse-width data signal stored in the pulse-width storage capacitor;

a first plate of the feedthrough capacitor is electrically connected to a third voltage terminal, and voltages supplied from the third voltage terminal comprise a third voltage value and a fourth voltage value that are different from each other; and

the working process of the pixel driving circuit further comprises a data-writing stage; and

the driving method comprises:

supplying a voltage having the third voltage value from the third voltage terminal in the data-writing stage; and

supplying a voltage having the fourth voltage value from the third voltage terminal in the light emission stage.