Semiconductor package
A semiconductor package including a first semiconductor chip including a first semiconductor layer having a first forward surface having a first integrated circuit thereon and a first rear surface and a plurality of first through vias electrically connected to the first integrated circuit and including at least first and second groups of first through vias, a second semiconductor chip including a second integrated circuit electrically connected to the first group of first through vias, and a third semiconductor chip including third through vias electrically connected to the second group of first through vias, wherein the first group of first through vias transfer input/output signals of the first integrated circuit, and the second group of first through vias transfer power to the first integrated circuit, may be provided.
1. A semiconductor package comprising:
a first semiconductor chip including,
a first semiconductor layer having a first forward surface and a first rear surface opposing the first forward surface, the first forward surface having a first integrated circuit thereon, and
a plurality of first through vias penetrating through the first semiconductor layer and electrically connected to the first integrated circuit, the plurality of first through vias including at least a first group of first through vias and a second group of first through vias;
a second semiconductor chip on the first rear surface of the first semiconductor chip, the second semiconductor chip including,
a second semiconductor layer having a second forward surface and a second rear surface opposing the second forward surface, the second forward surface having a second integrated circuit thereon, the second integrated circuit electrically connected to the first group of first through vias, and
second through vias penetrating through the second semiconductor layer and electrically connected to the second integrated circuit;
a third semiconductor chip on the first rear surface of the first semiconductor chip, the third semiconductor chip including,
a third semiconductor layer having a third forward surface and a third rear surface opposing the third forward surface, and
third through vias penetrating through at least parts of the third semiconductor layer and electrically connected to the second group of first through vias; and
a plurality of connection bumps on the second and third semiconductor chips and electrically connected to at least one of the second through vias and the third through vias,
wherein the first group of first through vias is configured to transfer input/output signals of the first integrated circuit, and the second group of first through vias is configured to transfer power to the first integrated circuit.
2. The semiconductor package of claim 1 , wherein the second forward surface of the second semiconductor chip faces the first rear surface of the first semiconductor chip.
3. The semiconductor package of claim 1 , wherein the second semiconductor chip further includes power through vias penetrating through the second semiconductor layer and configured to supply power to the second integrated circuit.
4. The semiconductor package of claim 1 , wherein a width of the first group of first through vias is equal to or smaller than that of the second group of first through vias.
5. The semiconductor package of claim 1 , wherein a width of each of the second through vias is equal to or smaller than that of each of the third through vias.
6. The semiconductor package of claim 1 , further comprising:
a first encapsulation layer on the first rear surface of the first semiconductor chip and covering side surfaces of each of the second and third semiconductor chips.
7. The semiconductor package of claim 6 , further comprising:
a second encapsulation layer between the plurality of connection bumps and the first encapsulation layer in a first direction perpendicular to the first forward surface, and between the second semiconductor chip and the third semiconductor chip in a second direction perpendicular to the first direction; and
a redistribution structure in the second encapsulation layer and electrically connecting the plurality of connection bumps to the second semiconductor chip and the third semiconductor chip.
8. The semiconductor package of claim 7 , wherein the first encapsulation layer and the second encapsulation layer include different materials.
9. The semiconductor package of claim 1 , wherein
the first integrated circuit includes a logic circuit, and
the second integrated circuit includes at least one of an input/output circuit, an analog circuit, a memory circuit, or a series-parallel conversion circuit for the logic circuit.
10. The semiconductor package of claim 9 , wherein the logic circuit includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an image signal processor (ISP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, or an application-specific integrated circuit (ASIC).
11. The semiconductor package of claim 9 , wherein the memory circuit includes at least one of a dynamic random access memory (DRAM), a static random access memory (SRAM), a phase changing random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), or a flash memory.
12. The semiconductor package of claim 1 , further comprising:
a fourth semiconductor chip on the first rear surface, the fourth semiconductor chip including a fourth semiconductor layer having a fourth forward surface and a fourth rear surface opposing the fourth forward surface, the fourth forward surface having a memory circuit electrically connected to the first integrated circuit thereon and,
wherein the plurality of first through vias further include a third group of first through vias electrically connecting the memory circuit and the first integrated circuit to each other.
13. The semiconductor package of claim 12 , wherein the memory circuit is electrically insulated from the plurality of connection bumps.
14. The semiconductor package of claim 12 , wherein the memory circuit includes a cache memory circuit.
15. The semiconductor package of claim 1 , wherein
the third forward surface of the third semiconductor chip faces the first rear surface, and
the third semiconductor chip further includes a circuit structure on the third forward surface, the circuit structure configured to electrically connect the third through vias and the second group of first through vias to each other.
16. A semiconductor package comprising:
a first semiconductor chip including,
a first semiconductor layer having a first forward surface and a first rear surface opposing the first forward surface, the first forward surface having a first integrated circuit thereon, and
a plurality of first through vias penetrating through the first semiconductor layer and electrically connected to the first integrated circuit, the plurality of first through vias divided into at least a first group of first through vias and a second group of first through vias;
a second semiconductor chip on the first rear surface of the first semiconductor chip, the second semiconductor chip including,
a second semiconductor layer having a second forward surface and a second rear surface opposing the second forward surface, the second forward surface having a second integrated circuit electrically connected to the first group of first through vias thereon, and
second through vias penetrating through the second semiconductor layer and electrically connected to the second integrated circuit; and
a third semiconductor chip on the first rear surface of the first semiconductor chip, the third semiconductor chip including,
a third semiconductor layer having a third forward surface and a third rear surface opposing the third forward surface, and
third through vias penetrating through at least parts of the third semiconductor layer and electrically connected to the second group of first through vias,
wherein a width of the first semiconductor chip in a first direction parallel to the first rear surface is equal to or greater than a sum of a width of the second semiconductor chip and a width of the third semiconductor chip in the first direction, and
the second group of first through vias and the third through vias are configured to supply power to the first integrated circuit.
17. The semiconductor package of claim 16 , wherein
the second and third semiconductor chips are provided as an integral semiconductor structure, and
the width of the first semiconductor chip in the first direction is greater than that of the integral semiconductor structure in the first direction.
18. The semiconductor package of claim 16 , wherein
the second and third semiconductor chips are provided as an integral semiconductor structure, and
the width of the first semiconductor chip in the first direction is same as that of the integral semiconductor structure in the first direction.
19. The semiconductor package of claim 16 , wherein the second semiconductor chip and the third semiconductor chip are spaced apart from each other in the first direction.
20. A semiconductor package comprising:
a first semiconductor chip including,
a first semiconductor layer having a first forward surface and a first rear surface opposing the first forward surface, the first forward surface having a first integrated circuit thereon, and
a plurality of first through vias penetrating through the first semiconductor layer and electrically connected to the first integrated circuit, the plurality of first through vias including at least a first group of first through vias, a second group of first through vias, and a third group of first through vias;
a second semiconductor chip including a second semiconductor layer, the second semiconductor chip being on the first semiconductor chip so that a second forward surface faces the first rear surface, the second semiconductor layer including,
the second forward surface and a second rear surface opposing the second forward surface, the second forward surface having a second integrated circuit electrically connected to the first group of first through vias thereon, and
second through vias penetrating through the second semiconductor layer and electrically connected to the second integrated circuit;
a third semiconductor chip including a third semiconductor layer, the third semiconductor chip being on the first semiconductor chip so that a third forward surface faces the first rear surface, the third semiconductor chip including,
the third forward surface and a third rear surface opposing the third forward surface, and
third through vias penetrating through the third semiconductor layer and electrically connected to the second group of first through vias; and
a fourth semiconductor chip including a fourth semiconductor layer, the fourth semiconductor layer being on the first semiconductor chip so that a fourth forward surface faces the first rear surface, the fourth semiconductor layer having the fourth forward surface and a fourth rear surface opposing the fourth forward surface, the fourth forward surface having a memory circuit electrically connected to the third group of first through vias thereon,
wherein the second semiconductor chip is configured to transfer input/output signals of the first integrated circuit, the third semiconductor chip is configured to supply power to the first integrated circuit, and the fourth semiconductor chip is configured to provide cache information to the first integrated circuit.