Memory device and method of manufacturing the same
A memory device and a method of manufacturing the memory device includes a stacked structure having a cell region and a slimming region. The memory device also includes a plurality of vertical channel structures each including memory cells and vertically passing through the stacked structure in the cell region. The memory device further includes a plurality of support structures each having a structure of each of the vertical channel structures and vertically passing through the stacked structure in the slimming region. The plurality of support structures have different heights depending on the shape of the stacked structure in the slimming region.
1. A memory device comprising:
a stacked structure having a cell region and a slimming region;
a plurality of vertical channel structures each including memory cells and a capping layer, vertically passing through the stacked structure in the cell region; and
a plurality of support structures each having a structure of each of the vertical channel structures and vertically passing through the stacked structure in the slimming region,
wherein the plurality of support structures have different heights depending on a shape of the stacked structure in the slimming region, and
wherein one or more of the plurality of support structures have the capping layer and others of the plurality of support structures do not have the capping layer.
2. The memory device according to claim 1 , wherein the stacked structure comprises first and second material layers alternately stacked on a base.
3. The memory device according to claim 2 ,
wherein the base comprises at least one of a semiconductor substrate, a peripheral circuit, and a source structure,
wherein the first material layer comprises an insulating layer, and
wherein the second material layer comprises a conductive layer.
4. The memory device according to claim 1 , wherein the stacked structure formed in the slimming region has a stepped structure.
5. The memory device according to claim 1 , wherein each of the support structures comprises a memory layer, a channel layer, and a vertical insulating layer that are sequentially formed along an inner surface of a vertical hole vertically passing through the stacked structure.
6. The memory device according to claim 5 , wherein the memory layer comprises a blocking layer, a trap layer, and a tunnel insulating layer that are sequentially formed in a hollow cylindrical shape along the inner surface of the vertical hole.
7. The memory device according to claim 6 ,
wherein each of the blocking layer and the tunnel insulating layer is formed of an insulating layer, and
wherein the trap layer is formed of material capable of trapping charges.
8. The memory device according to claim 5 ,
wherein the channel layer comprises a poly-silicon layer formed in a hollow cylindrical shape along an inner surface of the memory layer, and
wherein the vertical insulating layer comprises an insulating layer formed in a cylindrical shape inside the channel layer.
9. The memory device according to claim 1 , wherein the support structures have different heights depending on a height of the stacked structure.
10. A memory device comprising:
a first stacked structure defining a cell region and a slimming region;
a second stacked structure defining the cell region and the slimming region, wherein the second stacked structure is stacked on the first stacked structure;
a plurality of vertical channel structures passing through the first and the second stacked structures in the cell region; and
a plurality of support structures each having a structure of each of the vertical channel structures and passing through the first and the second stacked structures in the slimming region,
wherein the first stacked structure comprises first and second material layers alternately stacked over a base,
wherein the second stacked structure comprises third and fourth material layers alternately stacked on the first stacked structure,
wherein the second stacked structure in the slimming region has a stepped structure,
wherein the fourth material layer is exposed in the stepped structure, and
wherein the plurality of support structures have different heights depending on shapes of the first and the second stacked structures formed in the slimming region.
11. The memory device according to claim 10 , wherein, in the slimming region, the third and the fourth material layers are paired to form a stepped shape.
12. The memory device according to claim 10 , wherein the plurality of support structures have different heights depending on heights of the first and the second stacked structures formed in the slimming region.
13. The memory device according to claim 12 , wherein a height of a support structure is a length of the support structure from a bottom of the support structure to a top of the support structure.