Ferroelectric memory device and method of forming the same
A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.
1. A method of forming a ferroelectric memory device, comprising:
forming a multi-layer stack on a substrate, wherein the multi-layer stack comprises a plurality of dielectric layers and a plurality of conductive layers stacked alternately and has a trench penetrating therethrough;
introducing a Group III element precursor, a Group V element precursor and a transition metal precursor into a process chamber to form a III-V based ferroelectric layer on a sidewall of the trench; and
forming a channel layer on the III-V based ferroelectric layer.
2. The method of claim 1 , further comprising, after forming the III-V based ferroelectric layer and before forming the channel layer, performing an annealing process at a temperature of approximately 250° C. to approximately 400° C. in an oxygen containing or nitrogen containing ambient.
3. The method of claim 1 , further comprising, after forming the III-V based ferroelectric layer and before forming the channel layer, forming a hafnium based ferroelectric layer on the III-V based ferroelectric layer.
4. A method of forming a ferroelectric memory device, comprising:
forming a multi-layer stack on a substrate, wherein the multi-layer stack comprises a plurality of dielectric layers interleaved between a plurality of conductive layers;
forming one or more trenches extending through the multi-layer stack;
forming a III-V based ferroelectric layer on sidewalls of the multi-layer stack exposed by the one or more trenches by introducing a Group III element precursor, a Group V element precursor and a transition metal precursor into a process chamber, wherein the III-V based ferroelectric layer comprises at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements;
forming an oxide semiconductor layer on the III-V based ferroelectric layer; and
forming a conductive column within the one or more trenches, wherein the conductive column is separated from the III-V based ferroelectric layer by the oxide semiconductor layer.
5. The method of claim 4 , wherein the III-V based ferroelectric layer continuously extends past two or more of the plurality of conductive layers.
6. The method of claim 4 , wherein the at least one element selected from transition metal elements accounts for between 10 atomic percent and 40 atomic percent of the III-V based ferroelectric layer.
7. The method of claim 4 , wherein the III-V based ferroelectric layer comprises aluminum scandium nitride, aluminum yttrium nitride, gallium scandium nitride, or indium scandium nitride.
8. The method of claim 4 , wherein the III-V based ferroelectric layer comprises a hafnium based dielectric material.
9. The method of claim 4 , wherein the III-V based ferroelectric layer comprises a plurality of crystalline grains that are arranged onto one another in a column.
10. The method of claim 4 , wherein the III-V based ferroelectric layer is formed to continuously extend from a first sidewall contacting the plurality of conductive layers to a second sidewall contacting the oxide semiconductor layer.
11. The method of claim 4 , wherein the III-V based ferroelectric layer is a multi-layer structure comprising two III-V based materials and one non III-V layer between the two III-V based materials.
12. The method of claim 4 , further comprising:
forming a dielectric material on sidewalls of the oxide semiconductor layer, the dielectric material filling the one or more trenches;
patterning the dielectric material and the oxide semiconductor layer to form one or more openings extending through the dielectric material; and
forming one or more isolation pillars within the one or more openings.
13. The method of claim 12 , further comprising:
patterning the dielectric material after forming the isolation pillars to form an additional opening extending through the dielectric material; and
forming a conductive material within the additional opening to form the conductive column.
14. The method of claim 4 , wherein portions of the III-V based ferroelectric layer contacting the plurality of the conductive layers have first columnar-like grains with a long-axis direction perpendicular to a contacting surface of each of the plurality of conductive layers.
15. A method of forming a ferroelectric memory device, comprising:
forming a multi-layer stack on a substrate, wherein the multi-layer stack comprises a plurality of gate electrode layers and a plurality of dielectric layers stacked alternately;
patterning the multi-layer stack to form one or more trenches extending through the multi-layer stack;
forming a ferroelectric layer on sidewalls of the multi-layer stack exposed by the one or more trenches by introducing a Group III element precursor, a Group V element precursor, and a transition metal precursor into a process chamber, wherein portions of the ferroelectric layer contacting the plurality of gate electrode layers have first columnar-like grains with a long-axis direction perpendicular to a contacting surface of each of the plurality of gate electrode layers;
forming a channel layer on sidewalls of the ferroelectric layer;
forming an isolation pillar within the one or more trenches, the isolation pillar having opposing sidewalls contacting the ferroelectric layer along a first direction and being separated from a neighboring isolation pillar along a second direction; and
forming a conductive material along a side of the isolation pillar facing the second direction.
16. The method of claim 15 , wherein portions of the ferroelectric layer contacting the plurality of dielectric layers have second columnar-like grains with a second long-axis direction perpendicular to a contacting surface of each of the plurality of dielectric layers.
17. The method of claim 15 , wherein portions of the ferroelectric layer contacting the plurality of dielectric layers have second columnar-like grains with a second long-axis direction non-perpendicular to a contacting surface of each of the plurality of dielectric layers.
18. The method of claim 15 , wherein the portions of the ferroelectric layer contacting the plurality of gate electrode layers have a first grain dimension, portions of the ferroelectric layer contacting the plurality of dielectric layers have a second grain dimension different from the first grain dimension.
19. The method of claim 18 , wherein the second grain dimension is less than the first grain dimension.
20. The method of claim 18 , wherein the first grain dimension is 5-20 nm, and the second grain dimension is less than 1-5 nm.