Effective work function tuning via silicide induced interface dipole modulation for metal gates

1. A method, comprising:

providing a structure having a substrate and a channel layer over the substrate;

forming a high-k gate dielectric layer over the channel layer;

forming a work function metal layer over the high-k gate dielectric layer;

forming a silicide layer over the work function metal layer;

annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer;

removing the silicide layer; and

forming a bulk metal layer over the work function metal layer.

2. The method of claim 1 , further comprising:

forming an interfacial gate dielectric layer over the channel layer, wherein the high-k gate dielectric layer is formed over the interfacial gate dielectric layer.

3. The method of claim 1 , wherein the silicide layer includes titanium silicide, zirconium silicide, or yttrium silicide.

4. The method of claim 1 , wherein the work function metal layer has a thickness in a range of about 1 nm to about 1.5 nm.

5. The method of claim 1 , wherein the annealing is performed in a temperature in a range of about 550° C. to 600° C.

6. The method of claim 5 , wherein the temperature of the annealing and duration of the annealing are controlled such that about 1% to about 10% of the first portion of the work function metal layer is doped with Si.

7. The method of claim 1 , wherein the work function metal layer includes a nitride-based metallic material.

8. The method of claim 7 , wherein the work function metal layer includes TiN, TaN, WN, TiCN, TaCN, WCN, TiAlN, or TaAlN.

9. The method of claim 1 , wherein the work function metal layer includes TiN, the high-k gate dielectric layer includes HfO 2 , and the silicide layer includes titanium silicide, zirconium silicide, or yttrium silicide.

10. A method, comprising:

providing a structure having a substrate and first and second semiconductor channel layers over the substrate;

depositing a high-k gate dielectric layer over both the first and the second semiconductor channel layers;

forming a work function metal layer over the high-k gate dielectric layer and over both the first and the second semiconductor channel layers;

forming a silicide layer over the work function metal layer and over both the first and the second semiconductor channel layers;

patterning the silicide layer such that a first portion of the silicide layer remains over the first semiconductor channel and a second portion of the silicide layer over the second semiconductor channel is removed;

annealing the structure such that silicon elements from the silicide layer are driven into a portion of the work function metal layer that interfaces with the high-k gate dielectric layer; and

removing the first portion of the silicide layer.

11. The method of claim 10 , wherein the silicide layer includes titanium silicide, zirconium silicide, or yttrium silicide, the work function metal layer includes a nitride-based metallic material, and the high-k gate dielectric layer includes a hafnium-based dielectric material.

12. The method of claim 10 , after the removing of the first portion of the silicide layer, further comprising:

depositing a bulk metal layer over the work function metal layer and over both the first and the second semiconductor channel layers.

13. The method of claim 10 , wherein the work function metal layer has a thickness in a range of about 1 nm to about 1.5 nm.

14. The method of claim 10 , wherein the annealing is performed in a temperature in a range of about 550° C. to 600° C.

15. The method of claim 10 , wherein the patterning of the silicide layer includes:

forming an etch mask that covers the first portion of the silicide layer and exposes the second portion of the silicide layer;

etching the second portion of the silicide layer; and

after the etching of the second portion of the silicide layer, removing the etch mask.

16. A semiconductor structure, comprising:

a substrate;

a first semiconductor channel layer over the substrate;

a high-k gate dielectric layer over the first semiconductor channel layer;

a work function metal layer over the high-k gate dielectric layer, wherein a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon at a first dopant concentration; and

a bulk metal layer over the work function metal layer and interfacing with a second portion of the work function metal layer that is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration, wherein the bulk metal layer and the first and the second portions of the work function metal layer form at least a part of a first gate electrode, wherein the second dopant concentration is at least 10 times smaller than the first dopant concentration.

17. The semiconductor structure of claim 16 , further comprising:

a second semiconductor channel layer over the substrate, wherein the high-k gate dielectric layer, the work function metal layer, and the bulk metal layer are also disposed over the second semiconductor channel layer, wherein a third portion of the work function metal layer that is disposed over the second semiconductor channel layer is not doped with silicon.

18. The semiconductor structure of claim 16 , wherein the first dopant concentration is in a range of 1% to 10%.

19. The semiconductor structure of claim 16 , wherein the work function metal layer includes a nitride-based metallic material, and the high-k gate dielectric layer includes a hafnium-based dielectric material.

20. The semiconductor structure of claim 16 , wherein the second portion of the work function metal layer is doped with silicon at the second dopant concentration that is 0.1% or lower.