Methods, systems and apparatus for hybrid signal processing for pulse amplitude modulation
A method to implement hybrid signal processing includes steps for receiving an analog signal at a receiver frontend, sampling the received analog signal and storing the analog sampled signals using a plurality of sampling circuitries inside the receiver frontend. Then, processing the plurality of analog sampled signals using interleaved feed-forward equalizers (FFEs) to provide FFE interleaved sampled signal values corresponding to each of the sampling circuitries. Then, processing the analog sampled signals at an interleaved Decision Feedback Equalizer (DFE) to obtain DFE interleaved sampled signal values, summing each of the FFE interleaved sampled signal values with output from one of the DFE interleaved sampled signal values to provide equalizer output signal values, and digitizing the equalizer output signal values to provide digital data bits corresponding to each of the equalizer output signal values. Implementations of the method as a hybrid communication system, system-on-a-chip, and computer readable memory are also disclosed.
1. A method to implement hybrid signal processing, the method comprising:
receiving an analog signal at a receiver frontend;
sampling the received analog signal and storing the analog sampled signals using a plurality of sampling circuitries inside the receiver frontend;
processing the plurality of analog sampled signals at a plurality of interleaved feedforward equalizers (FFEs) to provide a plurality of FFE interleaved sampled signal values corresponding to each of the plurality of the sampling circuitries;
processing the plurality of analog sampled signals at an interleaved Decision Feedback Equalizer (DFE) to obtain a plurality of DFE interleaved sampled signal values;
summing each of the FFE interleaved sampled signal values with a corresponding output from one of the DFE interleaved sampled signal values to provide a plurality of equalizer output signal values; and
digitizing the plurality of equalizer output signals to provide digital data bits corresponding to each of the plurality of equalizer output signal values.
2. The method of claim 1 , wherein the analog signal is a continuous time-varying signal representing a pulse amplitude modulated signal.
3. The method of claim 1 , further comprising sampling the received analog signal at a sampling rate of 25G samples per second or higher.
4. The method of claim 1 , wherein the plurality of sampling circuitries receive and sample the received analog signal in parallel.
5. The method of claim 1 , wherein each sampling circuitry further comprising a Track-and-Hold (TAH) circuitry connected in series to a sample-and-hold (SAH) circuitry and configured to receive and hold a sampled signal value at the TAH circuitry during a first clock indicator and to transmit the sampled signal value to the SAH circuitry at a subsequent clock indicator.
6. The method of claim 5 , wherein the TAH tracks the received analog signal when the clock indicator is high and then holds the sampled signal value when the clock indicator is low.
7. The method of claim 5 , wherein processing the plurality of sampled-and-held signals further comprises determining a weighted sum of the samples from the SAH circuitries.
8. The method of claim 1 , further comprising digitizing the plurality of equalizer output signals at an interleaved M-bit Analog-to-Digital Converter (ADC), where M is a non-zero positive integer.
9. The method of claim 1 , further comprising digitizing the plurality of equalizer output signals to provide a digitized value corresponding to each of the plurality of equalizer output signal values.
10. The method of claim 1 , wherein the digitizing the plurality of equalizer output signals further comprises processing the plurality of equalizer output signals with an Analog-to-Digital converter to provide digital data bits corresponding to each of the plurality of equalizer output signal values.
11. At least one non-transitory machine-readable medium comprising instructions that, when executed by computing software, including a processor coupled to a memory circuitry, cause a communication system to:
receive an analog signal at a receiver frontend;
sample the received analog signal and store the analog sampled signals using a plurality of sampling circuitries inside the receiver frontend;
process the plurality of analog sampled signals at a plurality of interleaved feed-forward equalizers (FFEs) to provide a plurality of FFE interleaved sampled signal values corresponding to each of the plurality of the sampling circuitries;
process the plurality of analog sampled signals at an interleaved Decision Feedback Equalizer (DFE) to obtain a plurality of DFE interleaved sampled signal values;
sum each of the FFE interleaved sampled signal values with a corresponding output from one of the DFE interleaved sampled signal values to provide a plurality of equalizer output signal values; and
digitize the plurality of equalizer output signals to provide digital data bits corresponding to each of the plurality of equalizer output signal values.
12. The machine-readable medium of claim 11 , wherein the analog signal is a continuous time-varying signal representing a pulse amplitude modulated signal.
13. The machine-readable medium of claim 11 , further comprising sampling the received analog signal at a sampling rate of 25G samples per second or higher.
14. The machine-readable medium of claim 11 , wherein the plurality of sampling circuitries receive and sample the received analog signal in parallel.
15. The machine-readable medium of claim 11 , wherein each sampling circuitry further comprising a Track-and-Hold (TAH) circuitry connected in series to a sample-and-hold (SAH) circuitry and configured to receive and hold a sampled signal value at the TAH circuitry during a first clock indicator and to transmit the sampled signal value to the SAH circuitry at a subsequent clock indicator.
16. The machine-readable medium of claim 15 , wherein the TAH tracks the received analog signal when the clock indicator is high and then holds the sampled signal value when the clock indicator is low.
17. The machine-readable medium of claim 15 , wherein processing the plurality of sampled-and-held signals further comprises determining a weighted sum of the samples from the SAH circuitries.
18. The machine-readable medium of claim 11 , further comprising digitizing the plurality of equalizer output signals at an interleaved M-bit Analog-to-Digital Converter (ADC), where M is a non-zero positive integer.
19. The machine-readable medium of claim 11 , further comprising digitizing the plurality of equalizer output signals to provide a digitized value corresponding to each of the plurality of equalizer output signal values.
20. The machine-readable medium of claim 11 , wherein the digitizing the plurality of equalizer output signals further comprises processing the plurality of equalizer output signals with an Analog-to-Digital converter to provide digital data bits corresponding to each of the plurality of equalizer output signal values.
21. The machine-readable medium of claim 11 , wherein the communication system is implemented as a System-on-Chip having an integrated receiver frontend.
22. A hybrid communication system, comprising:
a receiver frontend to receive an analog signal;
a plurality of sampling circuities to sample the received analog signal;
a plurality of interleaved feed-forward equalizers (FFEs) to receive and process the analog sampled signals to provide a plurality of FFE interleaved sampled signal values corresponding to each of the plurality of the sampling circuitries;
an interleaved Decision Feedback Equalizer (DFE) to process the plurality of analog sampled signals to obtain a plurality of DFE interleaved sampled signal values;
a summer to sum each of the FFE interleaved sampled signal values with a corresponding output from one of the DFE interleaved sampled signal values to provide a plurality of equalizer output signal values; and
an analog-to-digital converter (ADC) to digitize the plurality of equalizer output signals to provide digital data bits corresponding to each of the plurality of equalizer output signal values.
23. The system of claim 22 , wherein the communication system is implemented as a System-on-Chip (SoC).
24. The system of claim 22 , wherein the plurality of sampling circuities are further configured to store the analog sampled signals.
25. The system of claim 22 , wherein the plurality of sampling circuitries are configured inside the receiver frontend.
26. The system of claim 22 , wherein the analog signal is a continuous time-varying signal representing a pulse amplitude modulated signal.
27. The system of claim 22 , wherein the sampling circuities sample the received analog signal at a sampling rate of 25G samples per second or higher.
28. The system of claim 22 , wherein the plurality of sampling circuitries receive and sample the received analog signal in parallel.
29. The system of claim 22 , wherein each of the sampling circuitries further comprises a Track-and-Hold (TAH) circuitry connected in series to a sample-and-hold (SAH) circuitry, each TAH configured to receive and hold a sampled signal value at the TAH circuitry during a first clock indicator and to transmit the sampled signal value to the SAH circuitry at a subsequent clock indicator.
30. The system of claim 29 , wherein the TAH tracks the received analog signal when the clock indicator is high and then holds the sampled signal value when the clock indicator is low or vice versa (low and high).
31. The system of claim 29 , further comprising a weighing circuitry to calculate a weighted sum of the samples from the SAH circuitries.
32. The system of claim 22 , wherein the ADC comprises an interleaved M-bit Analog-to-Digital Converter (ADC) to digitize the plurality of equalizer output signals, where M is a non-zero positive integer.
33. The system of claim 32 , wherein the interleaved M-bit ADC provides a plurality of digitized value corresponding to each of the plurality of equalizer output signal values.